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1. 发明授权

US5699298A Flash memory erase with controlled band-to-band tunneling current 失效
标题翻译：具有受控的带对隧道电流的闪存擦除
公开(公告)号：US5699298A
公开(公告)日：1997-12-16
申请号：US718525
申请日：1996-10-07
申请人： Tzeng-Huei Shiau , Ray-Lin Wan , Yuan-Chang Liu , Chun-Hsiung Hung , Weitong Chuang , Han Sung Chen , Fuchia Shone
发明人： Tzeng-Huei Shiau , Ray-Lin Wan , Yuan-Chang Liu , Chun-Hsiung Hung , Weitong Chuang , Han Sung Chen , Fuchia Shone
IPC分类号： G11C16/16 , G11C16/30 , G11C16/00
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/30
摘要： Substantial reduction in peak current encountered during an erase process for a flash memory device is achieved by selection of source voltage potential during the erase according to the expected band-to-band tunneling current encountered during the process. During the beginning of the process, a lower source voltage potential is selected, which is high enough to cause significant erasing while suppressing band-to-band tunneling current in a portion of the array, and during a second part of the erasing process, a higher source potential is utilized, which ensures successful erasing of the array, without exceeding the peak current requirements of the power supply used with the device. The first and second parts of the erase sequence will induce band-to-band tunneling current in addition to Fowler-Nordheim tunneling current. The band-to-band tunneling current is characterized by a turn on threshold source potential which is inversely related to the threshold of the cell receiving the voltage sequence. The source voltage used in the first part of the erase sequence is set at level that is near or above the turn on threshold source potential for higher threshold cells that are in the high threshold state, but less than the turn on threshold source potential for lower threshold cells in the high threshold state. The source potential in the second part is set at level which is near or above the turn on threshold source potential for lower threshold cells in the high threshold state.
摘要翻译： PCT No.PCT / US96 / 07490 Sec。 371日期1996年10月7日第 102（e）1996年10月7日PCT 1996年5月22日提交闪速存储器件的擦除过程中遇到的峰值电流的实质性降低是通过根据预期的带 - 带来在擦除期间选择源极电压电位来实现的过程中遇到的隧道电流。在该过程开始时，选择较低的源极电压电位，其足够高以引起显着擦除，同时抑制阵列的一部分中的带间隧穿电流，并且在擦除处理的第二部分期间，利用更高的源极电位，确保阵列的成功擦除，而不超过与器件一起使用的电源的峰值电流要求。擦除序列的第一部分和第二部分除了Fowler-Nordheim隧道电流之外还将引起带间隧穿电流。带 - 带隧穿电流的特征在于开启阈值源极电位，其与接收电压序列的电池的阈值成反比。在擦除序列的第一部分中使用的源电压被设置为接近或高于处于高阈值状态的较高阈值电池的阈值源极电位的接通或高于电平，但小于阈值源电位的导通电平较低阈值细胞处于高阈值状态。第二部分中的源极电位被设置在接近或高于阈值电位的阈值源电位的接通或高于在高阈值状态下的较低阈值电池的电位。

2. 发明授权

US5787039A Low current floating gate programming with bit-by-bit verification 失效
标题翻译：低电流浮栅编程与逐位验证
公开(公告)号：US5787039A
公开(公告)日：1998-07-28
申请号：US812615
申请日：1997-03-06
申请人： Han-Sung Chen , Tzeng-Huei Shiau , Yu-Shen Lin , Chung-Cheng Tsai , Jin-Lien Lin , Ray Lin Wan , Yuan-Chang Liu , Chun Hsiung Hung
发明人： Han-Sung Chen , Tzeng-Huei Shiau , Yu-Shen Lin , Chung-Cheng Tsai , Jin-Lien Lin , Ray Lin Wan , Yuan-Chang Liu , Chun Hsiung Hung
IPC分类号： G11C16/10 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3486 , G11C16/10 , G11C16/3459 , G11C16/3468
摘要： A system for programming arrays of floating gate memory cells reduces programming current requirements, and reduces wordline and bitline stress during programming. A word-to-be-programmed into a floating gate memory array is divided into a plurality of smaller subwords. Only one subword is programmed at a time, thereby reducing programming current requirements. Additionally, subwords which are successfully programmed are not reprogrammed even if bits in other subwords do not program properly. This creates less wordline stress than previous systems which program an entire word at once, thereby requiring subwords which program successfully to be reprogrammed along with subwords which fail to program. Finally, within each subword only those bits which failed to program are reprogrammed, thereby reducing bitline stress during reprogramming for those bits which were successfully programmed.
摘要翻译：用于编程浮动栅极存储器单元阵列的系统减少了编程电流要求，并且减少了编程期间的字线和位线应力。要被编程到浮动存储器阵列中的字被分成多个较小的子字。一次只编写一个子字，从而减少编程电流的要求。此外，即使其他子词的位未正确编程，成功编程的子词也不会被重新编程。这与以前系统一样编制整个单词的系统产生较少的字面压力，从而要求程序成功地重新编程的子词以及不能编程的子词。最后，在每个子字中，只有那些无法编程的位被重新编程，从而在对已成功编程的那些位的重新编程期间减少位线应力。

3. 发明授权

US5745410A Method and system for soft programming algorithm 失效
标题翻译：软编程算法的方法与系统
公开(公告)号：US5745410A
公开(公告)日：1998-04-28
申请号：US619485
申请日：1996-03-21
申请人： Tom Dang-Hsing Yiu , Fuchia Shone , I-Long Lee , Chia-Shing Chen , Hun-Song Chen , Yuan-Chang Liu , Tzeng-Huei Shiau , Kuen-Long Chang , Ray-Lin Wan
发明人： Tom Dang-Hsing Yiu , Fuchia Shone , I-Long Lee , Chia-Shing Chen , Hun-Song Chen , Yuan-Chang Liu , Tzeng-Huei Shiau , Kuen-Long Chang , Ray-Lin Wan
IPC分类号： G11C11/40
CPC分类号： G11C11/40
摘要： A floating gate memory device which includes control circuits to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block. This invention includes repairing the cells by applying a repair pulse to the cell's bit line while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.
摘要翻译： PCT No.PCT / US95 / 15051 Sec。 371日期1996年3月21日 102（e）1996年3月21日PCT 1995年11月17日PCT PCT。第WO97 / 19452号公报日期1997年5月29日一种浮动栅极存储器件，其包括产生修复脉冲以修复过擦除的单元的控制电路，使得它们可以逐块修复。本发明包括通过在维持字线电压高于地面的同时将修复脉冲施加到单元的位线来修复单元。在不同的实施例中，字线电压保持在地面以上两个不同的电压电平。在第一阶段，当施加修复脉冲时，字线电压保持在大约0.1伏和0.2伏之间大约100毫秒。在第二阶段，当施加修复脉冲时，字线电压保持在大约0.4伏和0.5伏之间大约100毫秒。

4. 发明授权

US06483045B1 Via plug layout structure for connecting different metallic layers 失效
标题翻译：通过插头布局结构连接不同的金属层
公开(公告)号：US06483045B1
公开(公告)日：2002-11-19
申请号：US09626409
申请日：2000-07-26
申请人： Mu-Chun Wang , Shih-Chieh Kao , Shiang Huang-Lu , Yuan-Chang Liu
发明人： Mu-Chun Wang , Shih-Chieh Kao , Shiang Huang-Lu , Yuan-Chang Liu
IPC分类号： H05K111
CPC分类号： H01L23/528 , H01L23/5226 , H01L2924/0002 , H05K1/115 , H05K2201/0769 , H05K2201/0969 , H05K2201/0979 , H01L2924/00
摘要： A via plug layout structure for connecting different metallic layers. The structure includes a plurality of via plugs arranged in a fan-shaped pattern and a plurality of empty bars positioned between a single via plug and the fanned-out via plugs so that incoming current to the single via plug is equally distributed to every one of the fanned-out via plug and current stress in each fanned-out via plug is identical. Hence, via plugs having particularly serious electromigration problem can be discovered. In addition, single via plug having different critical dimension can be fabricated so that maximum critical dimension sustainable by the via plug is determined after an electromigration test.
摘要翻译：用于连接不同金属层的通孔插头布局结构。该结构包括布置成扇形图案的多个通孔塞和位于单个通孔插头和扇形通孔之间的多个空杆，使得到单个通孔塞的进入电流被均等地分配到通过插头的每个扇形插头中的插头和电流应力都是相同的。因此，可以发现通过具有特别严重的电迁移问题的插头。此外，可以制造具有不同临界尺寸的单通孔塞，使得在电迁移测试之后确定由通孔插塞可持续的最大临界尺寸。

5. 发明授权

US08093916B2 Method of characterizing a semiconductor device and semiconductor device 失效
标题翻译：表征半导体器件和半导体器件的方法
公开(公告)号：US08093916B2
公开(公告)日：2012-01-10
申请号：US12478776
申请日：2009-06-05
申请人： Yue-Shiun Lee , Yuan-Chang Liu , Cheng-Hsiung Chen
发明人： Yue-Shiun Lee , Yuan-Chang Liu , Cheng-Hsiung Chen
IPC分类号： G01R31/26 , G01R31/02 , G21C17/00
CPC分类号： H01L29/4908 , G01R31/2648 , G01R31/2884
摘要： A method of characterizing semiconductor device includes providing a silicon-on-insulator (SOI) substrate with at least a body-tied (BT) SOI device and a BT dummy device for measurement, respectively measuring tunneling currents (Igb) and scattering parameters (S-parameters) of the BT SOI device and the BT dummy device, subtracting Igb of BT dummy device from that of the BT SOI device to obtain Igb of a floating body (FB) SOI device, filtering characteristics of the BT dummy device out to extract S-parameters of the FB SOI device, and analyzing the S-parameters of the FB SOI device to obtain gate-related capacitances of the FB SOI device.
摘要翻译：表征半导体器件的方法包括提供至少具有体结（BT）SOI器件和用于测量的BT虚拟器件的绝缘体上硅（SOI）衬底，分别测量隧道电流（Igb）和散射参数（S 参数）和BT虚拟器件，从BT SOI器件中减去BT伪器件的Igb以获得浮体（FB）SOI器件的Igb，将BT虚拟器件的滤波特性提取出来 FB SOI器件的S参数，并分析FB SOI器件的S参数，以获得FB SOI器件的栅极相关电容。

6. 发明申请

US20100315115A1 METHOD OF CHARACTERIZING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 失效
标题翻译：表征半导体器件和半导体器件的方法
公开(公告)号：US20100315115A1
公开(公告)日：2010-12-16
申请号：US12478776
申请日：2009-06-05
申请人： Yue-Shiun Lee , Yuan-Chang Liu , Cheng-Hsiung Chen
发明人： Yue-Shiun Lee , Yuan-Chang Liu , Cheng-Hsiung Chen
IPC分类号： G01R31/26 , H01L29/786
CPC分类号： H01L29/4908 , G01R31/2648 , G01R31/2884
摘要： A method of characterizing semiconductor device includes providing a silicon-on-insulator (SOI) substrate with at least a body-tied (BT) SOI device and a BT dummy device for measurement, respectively measuring tunneling currents (Igb) and scattering parameters (S-parameters) of the BT SOI device and the BT dummy device, subtracting Igb of BT dummy device from that of the BT SOI device to obtain Igb of a floating body (FB) SOI device, filtering characteristics of the BT dummy device out to extract S-parameters of the FB SOI device, and analyzing the S-parameters of the FB SOI device to obtain gate-related capacitances of the FB SOI device.
摘要翻译：表征半导体器件的方法包括提供至少具有体结（BT）SOI器件和用于测量的BT虚拟器件的绝缘体上硅（SOI）衬底，分别测量隧道电流（Igb）和散射参数（S 参数）和BT虚拟器件，从BT SOI器件中减去BT伪器件的Igb以获得浮体（FB）SOI器件的Igb，将BT虚拟器件的滤波特性提取出来 FB SOI器件的S参数，并分析FB SOI器件的S参数，以获得FB SOI器件的栅极相关电容。

7. 发明授权

US06878581B1 Electrostatic discharge protection structure and a method for forming the same 有权
标题翻译：静电放电保护结构及其形成方法
公开(公告)号：US06878581B1
公开(公告)日：2005-04-12
申请号：US09791099
申请日：2001-02-22
申请人： Yuan-Chang Liu , Mu-Chun Wang , Tien-Hao Tang
发明人： Yuan-Chang Liu , Mu-Chun Wang , Tien-Hao Tang
IPC分类号： H01L21/8234 , H01L27/02 , H01L21/8238
CPC分类号： H01L27/027 , H01L21/823418
摘要： A device structure and a method of fabricating an electrostatic discharge (ESD) protection circuit on a semiconductor device. A substrate is provided. A layer of silicon oxide is formed on the substrate. A photoresist mask is formed on the layer of silicon oxide. A species of n-type ions is implanted into the surface to form source/drain regions in the ESD protection area. After removing the photoresist, a metal layer is blanket deposited over the surface. A thermal process is performed to form salicide layers on the source/drain regions. A patterned photoresist is respectively formed to cover a portion of the salicide layer. An etching process is performed to strip away the exposed portion of the salicide layer.
摘要翻译：一种在半导体器件上制造静电放电（ESD）保护电路的器件结构和方法。提供基板。在衬底上形成一层氧化硅。在氧化硅层上形成光致抗蚀剂掩模。将一种n型离子注入表面以在ESD保护区域中形成源极/漏极区域。去除光致抗蚀剂后，金属层被覆盖在表面上。进行热处理以在源极/漏极区域上形成自对准硅化物层。分别形成图案化的光致抗蚀剂以覆盖自对准硅化物层的一部分。执行蚀刻处理以剥离自对准硅化物层的暴露部分。

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