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1. 发明申请

US20070178681A1 SEMICONDUCTOR DEVICE HAVING A PLURALITY OF METAL LAYERS DEPOSITED THEREON 审中-公开
标题翻译：具有多孔金属层的半导体器件
公开(公告)号：US20070178681A1
公开(公告)日：2007-08-02
申请号：US11621589
申请日：2007-01-10
申请人： Young-su CHUNG , Sung-kee HAN , Hyung-suk JUNG , Hyung-ik LEE
发明人： Young-su CHUNG , Sung-kee HAN , Hyung-suk JUNG , Hyung-ik LEE
IPC分类号： H01L21/20
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/28194 , H01L29/517 , H01L29/78
摘要： A semiconductor device has a plurality of stacked metal layers. The semiconductor device includes a substrate, a gate oxide layer deposited on the substrate and formed from a high-k dielectric material, a first metal layer deposited on the gate oxide layer and formed from a nitride of a metal of the high-k dielectric material of the gate oxide layer, a second metal layer deposited on the first metal layer, a third metal layer deposited on the second metal layer, and a material layer deposited on the third metal layer, wherein the material layer taken together with the first, second and third metal layers forms a gate electrode. Because any chemical reaction between the gate oxide layer and the metal layer can be controlled, deterioration of the capacitance equivalent oxide thickness) and leakage of current are prevented, and a semiconductor device having improved insulation can be provided.
摘要翻译：半导体器件具有多个堆叠的金属层。半导体器件包括衬底，沉积在衬底上并由高k电介质材料形成的栅极氧化物层，沉积在栅极氧化物层上并由高k电介质材料的金属的氮化物形成的第一金属层栅极氧化物层，沉积在第一金属层上的第二金属层，沉积在第二金属层上的第三金属层和沉积在第三金属层上的材料层，其中材料层与第一，第二金属层并且第三金属层形成栅电极。由于可以控制栅氧化层和金属层之间的任何化学反应，所以可以防止电容当量氧化物厚度的劣化）和电流泄漏，并且可以提供绝缘性提高的半导体器件。

2. 发明申请

US20070152283A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070152283A1
公开(公告)日：2007-07-05
申请号：US11551994
申请日：2006-10-23
申请人： Hion-suck BAIK , Eun-ha LEE , Hyung-suk JUNG , Sung-kee HAN , Min-ho YANG
发明人： Hion-suck BAIK , Eun-ha LEE , Hyung-suk JUNG , Sung-kee HAN , Min-ho YANG
IPC分类号： H01L29/94 , H01L21/3205
CPC分类号： H01L21/28556 , H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device and a manufacturing method thereof for preventing gate electrode degradation and gate current leakage. The semiconductor device includes a gate insulating layer including an H-k (high dielectric) material on a semiconductor substrate, a barrier metal layer including a metal alloy on the gate insulating layer, and a gate electrode layer formed on the barrier metal layer. Illustratively, the barrier metal layer includes at least one of TaAlN (tantalum aluminum nitride) or TiAlN (titanium aluminum nitride). The barrier metal layer can include an oxidation-resistant material so that oxidation of the barrier metal layer is prevented during a subsequent annealing of the semiconductor device in an oxygen atmosphere. Thus, degradation of a gate electrode is prevented, and gate current leakage due to degradation of the gate electrode is prevented.
摘要翻译：一种用于防止栅电极劣化和栅极电流泄漏的半导体器件及其制造方法。半导体器件包括在半导体衬底上包括H-k（高电介质）材料的栅极绝缘层，在栅极绝缘层上包括金属合金的阻挡金属层和形成在阻挡金属层上的栅电极层。说明性地，阻挡金属层包括TaAlN（氮化钽）或TiAlN（氮化铝）中的至少一种。阻挡金属层可以包括抗氧化材料，从而在半导体器件在氧气氛中的随后的退火中防止了阻挡金属层的氧化。因此，防止了栅电极的劣化，并且防止了由于栅电极的劣化引起的栅极电流泄漏。

3. 发明申请

US20110193181A1 SEMICONDUCTOR DEVICE HAVING DIFFERENT METAL GATE STRUCTURES 审中-公开
标题翻译：具有不同金属门结构的半导体器件
公开(公告)号：US20110193181A1
公开(公告)日：2011-08-11
申请号：US13089603
申请日：2011-04-19
申请人： Hyung-suk JUNG , Jong-ho LEE , Sung-kee HAN , Ha-jin LIM
发明人： Hyung-suk JUNG , Jong-ho LEE , Sung-kee HAN , Ha-jin LIM
IPC分类号： H01L29/772
CPC分类号： H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/02362 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L21/3142 , H01L21/31645 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A semiconductor includes a channel region in a semiconductor substrate, a gate dielectric film on the channel region, and a gate on the gate dielectric film. The gate includes a doped metal nitride film, formed from a nitride of a first metal and doped with a second metal which is different from the first metal, and a conductive polysilicon layer formed on the doped metal nitride film. The gate may further include a metal containing capping layer interposed between the doped metal nitride film and the conductive polysilicon layer.
摘要翻译：半导体包括半导体衬底中的沟道区域，沟道区上的栅极电介质膜和栅极电介质膜上的栅极。栅极包括由第一金属的氮化物形成并掺杂有与第一金属不同的第二金属的掺杂金属氮化物膜和形成在掺杂金属氮化物膜上的导电多晶硅层。栅极还可以包括插入在掺杂的金属氮化物膜和导电多晶硅层之间的含金属的覆盖层。

4. 发明申请

US20080067606A1 SEMICONDUCTOR DEVICE HAVING DIFFERENT METAL GATE STRUCTURES 有权
标题翻译：具有不同金属门结构的半导体器件
公开(公告)号：US20080067606A1
公开(公告)日：2008-03-20
申请号：US11946153
申请日：2007-11-28
申请人： Hyung-suk JUNG , Jong-ho LEE , Sung-kee HAN , Ha-jin LIM
发明人： Hyung-suk JUNG , Jong-ho LEE , Sung-kee HAN , Ha-jin LIM
IPC分类号： H01L29/78
CPC分类号： H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/02362 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L21/3142 , H01L21/31645 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A semiconductor includes a channel region in a semiconductor substrate, a gate dielectric film on the channel region, and a gate on the gate dielectric film. The gate includes a doped metal nitride film, formed from a nitride of a first metal and doped with a second metal which is different from the first metal, and a conductive polysilicon layer formed on the doped metal nitride film. The gate may further include a metal containing capping layer interposed between the doped metal nitride film and the conductive polysilicon layer.
摘要翻译：半导体包括半导体衬底中的沟道区域，沟道区上的栅极电介质膜和栅极电介质膜上的栅极。栅极包括由第一金属的氮化物形成并掺杂有与第一金属不同的第二金属的掺杂金属氮化物膜和形成在掺杂金属氮化物膜上的导电多晶硅层。栅极还可以包括插入在掺杂的金属氮化物膜和导电多晶硅层之间的含金属的覆盖层。

5. 发明申请

US20160133632A1 INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：集成电路装置及其制造方法
公开(公告)号：US20160133632A1
公开(公告)日：2016-05-12
申请号：US14853442
申请日：2015-09-14
申请人： Hong-bae PARK , Ja-hum KU , Myeong-cheol KIM , Jin-wook LEE , Sung-kee HAN
发明人： Hong-bae PARK , Ja-hum KU , Myeong-cheol KIM , Jin-wook LEE , Sung-kee HAN
IPC分类号： H01L27/11 , H01L27/02 , H01L27/092
CPC分类号： H01L27/1104 , H01L21/02164 , H01L21/0217 , H01L21/823821 , H01L21/823828 , H01L21/823871 , H01L21/823878 , H01L23/528 , H01L27/0207 , H01L27/0924 , H01L29/0649 , H01L29/66545 , H01L29/6656 , H01L29/785
摘要： A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.
摘要翻译：一种方法包括在衬底上提供多个有源区，以及在所述多个有源区中的两个之间的至少第一器件隔离层，其中所述多个有源区在第一方向上延伸; 提供沿第二方向延伸的栅极层，所述栅极层形成多条栅极线，所述栅极线包括相对于彼此以直线延伸的第一栅极线和第二栅极线，所述第二栅极线和第二栅极线之间具有间隔，所述第一栅极线和第二栅极线交叉有效区域中的至少一个，提供覆盖第一器件隔离层并围绕第一和第二栅极线周围的有源区域覆盖的绝缘层; 以及在所述第一栅极线和所述第二栅极线之间的空间中提供栅极间绝缘区域。

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