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1. 发明申请

US20120146830A1 ANALOG DIGITAL CONVERTER 有权
标题翻译：模拟数字转换器
公开(公告)号：US20120146830A1
公开(公告)日：2012-06-14
申请号：US13243267
申请日：2011-09-23
申请人： Young-deuk JEON , Young Kyun CHO , Jaewon NAM , Jong-Kee KWON
发明人： Young-deuk JEON , Young Kyun CHO , Jaewon NAM , Jong-Kee KWON
IPC分类号： H03M1/12
CPC分类号： H03M1/164 , H03M1/468
摘要： Provided is an analog digital converter (ADC). The ADC includes: a capacitor array generating a level voltage; a comparator outputting a compare signal by comparing the level voltage; and a logic circuit determining digital bits of an analog signal based on the compare signal, wherein the logic circuit determines at least one digital bit among digital bits of the analog signal while a sampling operation of the analog signal is performed in the capacitor array.
摘要翻译：提供了一种模拟数字转换器（ADC）。 ADC包括：产生电平电压的电容器阵列; 比较器，通过比较电平电压输出比较信号; 以及逻辑电路，其基于所述比较信号确定模拟信号的数字位，其中所述逻辑电路在所述电容器阵列中执行所述模拟信号的采样操作时，确定所述模拟信号的数字位中的至少一个数字位。

2. 发明申请

US20100066583A1 MULTI-STAGE SUCCESSIVE APPROXIMATION REGISTER ANALOG-TODIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERTING METHOD USING THE SAME 有权
标题翻译：多级连续逼近寄存器模拟转换器和使用该模拟转换器的模拟数字转换方法
公开(公告)号：US20100066583A1
公开(公告)日：2010-03-18
申请号：US12433764
申请日：2009-04-30
申请人： Young Deuk JEON , Young Kyun CHO , Jae Won NAM , Jong Kee KWON
发明人： Young Deuk JEON , Young Kyun CHO , Jae Won NAM , Jong Kee KWON
IPC分类号： H03M1/38
CPC分类号： H03M1/164 , H03M1/468
摘要： A multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and an analog-to-digital converting method using the same are provided. The multi-stage SAR ADC connects small-size and low-power SAR ADCs in multiple stages, thereby reducing a whole chip size and power consumption. The analog-to-digital converting method simultaneously performs analog-to-digital conversions in the SAR ADCs connected in the multiple stages, thereby reducing an analog-to-digital conversion time and maintaining an operating rate of several tens of MHz to several hundreds of MHz similar to that of a pipeline ADC.
摘要翻译：提供了多级连续近似寄存器模数转换器（SAR ADC）和使用其的模数转换方法。多级SAR ADC多级连接小尺寸和低功耗SAR ADC，从而降低整个芯片尺寸和功耗。模数转换方法同时在多级连接的SAR ADC中执行模数转换，从而减少模数转换时间，并将几十MHz至几百 MHz与流水线ADC类似。

3. 发明申请

US20100085229A1 ALGORITHMIC ANALOG-TO-DIGITAL CONVERTER 失效
标题翻译：算术模拟数字转换器
公开(公告)号：US20100085229A1
公开(公告)日：2010-04-08
申请号：US12433780
申请日：2009-04-30
申请人： Jae Won NAM , Young Deuk JEON , Young Kyun CHO , Jong Kee KWON
发明人： Jae Won NAM , Young Deuk JEON , Young Kyun CHO , Jong Kee KWON
IPC分类号： H03M1/12
CPC分类号： H03M1/162
摘要： Provided is an algorithmic analog-to-digital converter (ADC). In the algorithmic ADC, the number of preprocessing amplifiers used in a flash ADC is reduced by sharing the preprocessing amplifiers in the flash ADC, and thus chip size can be reduced. In addition, power consumption can be reduced by dynamically decreasing the bandwidth of an operational amplifier included in a multiplying digital-to-analog converter (MDAC) according to a required resolution.
摘要翻译：提供了一种算法模数转换器（ADC）。在算法ADC中，通过在闪存ADC中共享预处理放大器来减少闪存ADC中使用的预处理放大器的数量，从而可以减少芯片尺寸。此外，可以通过根据所需分辨率动态地减小包括在乘法数模转换器（MDAC）中的运算放大器的带宽来降低功耗。

4. 发明申请

US20110018605A1 OFFSET-VOLTAGE CALIBRATION CIRCUIT 失效
标题翻译：偏移校准电路
公开(公告)号：US20110018605A1
公开(公告)日：2011-01-27
申请号：US12843535
申请日：2010-07-26
申请人： Young Kyun CHO , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
发明人： Young Kyun CHO , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
IPC分类号： H03L5/00
CPC分类号： H03M1/1023 , H03M1/66
摘要： Provided is an offset-voltage calibration circuit. The circuit includes a comparator configured to receive at least two comparison voltages and output a result of a comparison between the comparison voltages, an up/down counter (UDC) configured to output an up-counting or down-counting output signal in response to an output signal of the comparator, and a current digital-to-analog converter (DAC) configured to control the amount of current supplied from a node to which the comparison voltage is applied, in response to the output signal of the UDC and control the magnitude of the comparison voltage.
摘要翻译：提供了一种偏移电压校准电路。所述电路包括比较器，被配置为接收至少两个比较电压并输出所述比较电压之间的比较结果;响应于所述比较电压被配置为输出递增计数或递减计数输出信号的上/下计数器（UDC）比较器的输出信号，以及被配置为响应于UDC的输出信号来控制从施加了比较电压的节点提供的电流量的电流数模转换器（DAC），并且控制幅度的比较电压。

5. 发明申请

US20090091387A1 SWITCHED-CAPACITOR VARIABLE GAIN AMPLIFIER HAVING HIGH VOLTAGE GAIN LINEARITY 失效
标题翻译：具有高电压增益线性的开关电容器可变增益放大器
公开(公告)号：US20090091387A1
公开(公告)日：2009-04-09
申请号：US12195212
申请日：2008-08-20
申请人： Young Kyun CHO , Young Deuk Jeon , Jong Kee Kwon , Jong Dae Kim
发明人： Young Kyun CHO , Young Deuk Jeon , Jong Kee Kwon , Jong Dae Kim
IPC分类号： H03G3/30
CPC分类号： H03G1/0094 , H03F3/005 , H03F3/45475
摘要： Provided is a switched-capacitor variable gain amplifier having high voltage gain linearity. According to the above amplifier, a sampling capacitor is shared and used at a sampling phase and an amplification phase, and thus a voltage gain error caused by capacitor mismatch can be reduced. Also, using a unit capacitor array enables circuit design and layout to be simplified. Further, in the amplifier, a voltage gain can be easily controlled to be more or less than 1, as necessary, and power consumption and kT/C noise can be reduced by a feedback factor that is relatively large, so that gain amplification performance can be improved.
摘要翻译：提供了具有高电压增益线性度的开关电容器可变增益放大器。根据上述放大器，采样电容器在采样相位和放大阶段被共享并使用，因此可以减小由电容器失配引起的电压增益误差。此外，使用单位电容阵列可以简化电路设计和布局。此外，在放大器中，根据需要，可以容易地将电压增益控制为大于或等于1，并且可以通过相对较大的反馈因子来降低功耗和kT / C噪声，从而增益放大性能可以要改进

6. 发明申请

US20090033530A1 METHOD OF CONTROLLING PIPELINE ANALOG-TO-DIGITAL CONVERTER AND PIPELINE ANALOG-TO-DIGITAL CONVERTER IMPLEMENTING THE SAME 有权
标题翻译：管道模拟数字转换器和管道数字转换器的控制方法
公开(公告)号：US20090033530A1
公开(公告)日：2009-02-05
申请号：US12027495
申请日：2008-02-07
申请人： Young Deuk JEON , Young Kyun CHO , Kwi Dong KIM , Jong Kee KWON , Jong Dae KIM , Seung Chul LEE
发明人： Young Deuk JEON , Young Kyun CHO , Kwi Dong KIM , Jong Kee KWON , Jong Dae KIM , Seung Chul LEE
IPC分类号： H03M1/00
CPC分类号： H03M1/1245 , H03M1/002 , H03M1/44
摘要： Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC.
摘要翻译：提供了没有前端采样保持放大器（SHA）的管线模数转换器（ADC）及其控制方法。该方法包括以下步骤：在ADC和包括在第一级中的残余信号发生器同时对模拟输入信号进行采样，并分别产生第一采样值和第二采样值; 在剩余信号发生器处保持第二采样值，并且同时在ADC处放大并转换第一采样值为相应的数字代码; 以及在剩余信号发生器处产生使用数字码的残留信号。流水线ADC和控制相同的方法最小化了通过去除前端SHA引起的采样失配，从而确保了没有前端SHA的稳定性能。由于不使用前端SHA，因此可以减少芯片尺寸和功耗，并提高ADC的性能。

7. 发明申请

US20120242266A1 SENSORLESS BLDC MOTOR SYSTEMS AND DRIVING METHODS OF SENSORLESS BLDC MOTOR 有权
标题翻译：无传感器BLDC电动机的传感器和驱动方法
公开(公告)号：US20120242266A1
公开(公告)日：2012-09-27
申请号：US13347128
申请日：2012-01-10
申请人： Young Kyun CHO , Hui Dong LEE , Jaewon NAM , Jong-Kee KWON
发明人： Young Kyun CHO , Hui Dong LEE , Jaewon NAM , Jong-Kee KWON
IPC分类号： H02P6/18
CPC分类号： H02P6/142 , H02P6/15
摘要： Provided is a sensorless BLDC motor system. The sensorless BLDC motor system includes a BLDC motor, a comparator, a motor controller, a three-phase inverter, and a mode selector. The BLDC motor includes first to third coils. The comparator compares a voltage of a specific coil of the first to third coils with a neutral-point voltage to output the compared result. The voltage of the specific coil becomes equal to the neutral-point voltage and a specific time elapses, and then the motor controller generates first and second coil control signals based on the compared result. The three-phase inverter supplies a source voltage or ground voltage to the specific coil, or floats the specific coil, in response to the first and second coil control signals. The mode selector selects a driving mode of the BLDC motor by adjusting the specific time.
摘要翻译：提供无传感器BLDC电机系统。无传感器BLDC电机系统包括BLDC电机，比较器，电机控制器，三相逆变器和模式选择器。 BLDC电机包括第一至第三线圈。比较器将第一至第三线圈的特定线圈的电压与中性点电压进行比较，以输出比较结果。特定线圈的电压等于中性点电压，经过一定时间，然后电机控制器根据比较结果产生第一和第二线圈控制信号。三相逆变器响应于第一和第二线圈控制信号向特定线圈提供源极电压或接地电压，或者浮动特定线圈。模式选择器通过调整具体时间来选择BLDC电机的驱动模式。

8. 发明申请

US20130135126A1 SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND OPERATION METHOD THEREOF 失效
标题翻译：后续逼近寄存器模拟数字转换器及其操作方法
公开(公告)号：US20130135126A1
公开(公告)日：2013-05-30
申请号：US13531418
申请日：2012-06-22
申请人： Young Kyun CHO , Jae Ho JUNG
发明人： Young Kyun CHO , Jae Ho JUNG
IPC分类号： H03M1/38
CPC分类号： H03M1/462 , H03M1/468
摘要： Provided are a successive approximation register analog-to-digital converter and an operation method thereof. The method includes latching input signals which respectively correspond to bits of a first series of bits as digital data by directly transmitting the input signals to a latch; latching input signals which respectively correspond to bits of a second series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a first period of amplification by using a preamplifier; and latching input signals which respectively correspond to bits of a third series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a second period of amplification by using the preamplifier.
摘要翻译：提供了逐次逼近寄存器模数转换器及其操作方法。该方法包括通过将输入信号直接发送到锁存器来将分别对应于第一位数位的输入信号锁定为数字数据; 通过使用前置放大器在放大的第一周期期间放大输入信号之后，通过将输入信号发送到锁存器来将分别对应于第二位数位的输入信号锁存为数字数据; 以及通过使用前置放大器在放大的第二周期期间放大输入信号之后，通过将输入信号发送到锁存器来将分别对应于第三比特位的输入信号锁存为数字数据。

9. 发明申请

US20100019321A1 MULTIPLE-GATE MOS TRANSISTOR USING Si SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：使用Si衬底的多门MOS晶体管及其制造方法
公开(公告)号：US20100019321A1
公开(公告)日：2010-01-28
申请号：US12556666
申请日：2009-09-10
申请人： Young Kyun CHO , Tae Moon ROH , Jong Dae KIM
发明人： Young Kyun CHO , Tae Moon ROH , Jong Dae KIM
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/7851
摘要： Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region.
摘要翻译：提供一种多栅极MOS（金属氧化物半导体）晶体管及其制造方法。晶体管包括具有通道区域的单晶有源区域，沟道区域具有通过用压花图案图案化体硅衬底的上部并且具有比沟道区域更厚和更宽的面积而获得的流线型形状（∩）的上部 ; 形成在所述单晶有源区的两个侧表面处的氮化物层，以在预定高度暴露所述单晶有源区的上部; 以及形成为与通道区域的单晶有源区域的暴露的上部分重叠的栅电极。

10. 发明申请

US20080135935A1 DUAL STRUCTURE FINFET AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：双结构FINFET及其制造方法
公开(公告)号：US20080135935A1
公开(公告)日：2008-06-12
申请号：US11924903
申请日：2007-10-26
申请人： Young Kyun CHO , Tae Moon ROH , Jong Dae KIM
发明人： Young Kyun CHO , Tae Moon ROH , Jong Dae KIM
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： Provided are a dual structure FinFET and a method of fabricating the same. The FinFET includes: a lower device including a lower silicon layer formed on a substrate and a gate electrode vertically formed on the substrate; an upper device including an upper silicon layer formed on the lower device and the vertically formed gate electrode; and a first solid source material layer, a solid source material interlayer insulating layer, and a second solid source material layer sequentially formed between the lower silicon layer and the upper silicon layer. Therefore, the FinFET can be provided which enhances the density of integration of a circuit, suppresses thin film damages due to ion implantation using solid phase material layers, and has a stabilized characteristic by a simple and low-cost process. Also, mobility of an upper device can be improved to enhance current drivability of the upper device, isolation can be implemented through a buried oxide layer to reduce an effect due to a field oxide layer, and raised source and drain can be implemented to reduce serial resistance components of the source and drain to increase current drivability.
摘要翻译：提供了一种双重结构的FinFET及其制造方法。 FinFET包括：下部器件，包括形成在衬底上的下硅层和垂直形成在衬底上的栅电极; 上部器件，包括形成在下部器件上的上硅层和垂直形成的栅电极; 以及顺序地形成在下硅层和上硅层之间的第一固体源材料层，固体源材料层间绝缘层和第二固体源材料层。因此，可以提供FinFET，其增强电路的集成密度，抑制由于使用固相材料层的离子注入引起的薄膜损伤，并且通过简单且低成本的工艺具有稳定的特性。此外，可以提高上部器件的迁移率以增强上部器件的电流驱动能力，可以通过掩埋氧化物层实现隔离，以减少由于场氧化物层引起的影响，并且可以实现升高的源极和漏极以减少串联源极和漏极的电阻分量以增加电流驱动能力。

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