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1. 发明申请

US20100085229A1 ALGORITHMIC ANALOG-TO-DIGITAL CONVERTER 失效
标题翻译：算术模拟数字转换器
公开(公告)号：US20100085229A1
公开(公告)日：2010-04-08
申请号：US12433780
申请日：2009-04-30
申请人： Jae Won NAM , Young Deuk JEON , Young Kyun CHO , Jong Kee KWON
发明人： Jae Won NAM , Young Deuk JEON , Young Kyun CHO , Jong Kee KWON
IPC分类号： H03M1/12
CPC分类号： H03M1/162
摘要： Provided is an algorithmic analog-to-digital converter (ADC). In the algorithmic ADC, the number of preprocessing amplifiers used in a flash ADC is reduced by sharing the preprocessing amplifiers in the flash ADC, and thus chip size can be reduced. In addition, power consumption can be reduced by dynamically decreasing the bandwidth of an operational amplifier included in a multiplying digital-to-analog converter (MDAC) according to a required resolution.
摘要翻译：提供了一种算法模数转换器（ADC）。在算法ADC中，通过在闪存ADC中共享预处理放大器来减少闪存ADC中使用的预处理放大器的数量，从而可以减少芯片尺寸。此外，可以通过根据所需分辨率动态地减小包括在乘法数模转换器（MDAC）中的运算放大器的带宽来降低功耗。

2. 发明申请

US20100066583A1 MULTI-STAGE SUCCESSIVE APPROXIMATION REGISTER ANALOG-TODIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERTING METHOD USING THE SAME 有权
标题翻译：多级连续逼近寄存器模拟转换器和使用该模拟转换器的模拟数字转换方法
公开(公告)号：US20100066583A1
公开(公告)日：2010-03-18
申请号：US12433764
申请日：2009-04-30
申请人： Young Deuk JEON , Young Kyun CHO , Jae Won NAM , Jong Kee KWON
发明人： Young Deuk JEON , Young Kyun CHO , Jae Won NAM , Jong Kee KWON
IPC分类号： H03M1/38
CPC分类号： H03M1/164 , H03M1/468
摘要： A multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and an analog-to-digital converting method using the same are provided. The multi-stage SAR ADC connects small-size and low-power SAR ADCs in multiple stages, thereby reducing a whole chip size and power consumption. The analog-to-digital converting method simultaneously performs analog-to-digital conversions in the SAR ADCs connected in the multiple stages, thereby reducing an analog-to-digital conversion time and maintaining an operating rate of several tens of MHz to several hundreds of MHz similar to that of a pipeline ADC.
摘要翻译：提供了多级连续近似寄存器模数转换器（SAR ADC）和使用其的模数转换方法。多级SAR ADC多级连接小尺寸和低功耗SAR ADC，从而降低整个芯片尺寸和功耗。模数转换方法同时在多级连接的SAR ADC中执行模数转换，从而减少模数转换时间，并将几十MHz至几百 MHz与流水线ADC类似。

3. 发明申请

US20090033530A1 METHOD OF CONTROLLING PIPELINE ANALOG-TO-DIGITAL CONVERTER AND PIPELINE ANALOG-TO-DIGITAL CONVERTER IMPLEMENTING THE SAME 有权
标题翻译：管道模拟数字转换器和管道数字转换器的控制方法
公开(公告)号：US20090033530A1
公开(公告)日：2009-02-05
申请号：US12027495
申请日：2008-02-07
申请人： Young Deuk JEON , Young Kyun CHO , Kwi Dong KIM , Jong Kee KWON , Jong Dae KIM , Seung Chul LEE
发明人： Young Deuk JEON , Young Kyun CHO , Kwi Dong KIM , Jong Kee KWON , Jong Dae KIM , Seung Chul LEE
IPC分类号： H03M1/00
CPC分类号： H03M1/1245 , H03M1/002 , H03M1/44
摘要： Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC.
摘要翻译：提供了没有前端采样保持放大器（SHA）的管线模数转换器（ADC）及其控制方法。该方法包括以下步骤：在ADC和包括在第一级中的残余信号发生器同时对模拟输入信号进行采样，并分别产生第一采样值和第二采样值; 在剩余信号发生器处保持第二采样值，并且同时在ADC处放大并转换第一采样值为相应的数字代码; 以及在剩余信号发生器处产生使用数字码的残留信号。流水线ADC和控制相同的方法最小化了通过去除前端SHA引起的采样失配，从而确保了没有前端SHA的稳定性能。由于不使用前端SHA，因此可以减少芯片尺寸和功耗，并提高ADC的性能。

4. 发明申请

US20090096646A1 METHOD OF ALGORITHMIC ANALOG-TO-DIGITAL CONVERSION AND ALGORITHMIC ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：算法模拟数字转换和算法模数转换器的方法
公开(公告)号：US20090096646A1
公开(公告)日：2009-04-16
申请号：US12198837
申请日：2008-08-26
申请人： Seung Chul LEE , Jae Won NAM , Young Deuk JEON , Jong Kee KWON
发明人： Seung Chul LEE , Jae Won NAM , Young Deuk JEON , Jong Kee KWON
IPC分类号： H03M1/12
CPC分类号： H03M1/1225 , H03M1/167
摘要： Provided are a method of algorithmic analog-to-digital conversion and an algorithmic Analog-to-Digital Converter (ADC). The algorithmic ADC includes a Multiplying Digital-to-Analog Converter (MDAC). The MDAC includes a Digital-to-Analog Converter (DAC) for converting a first digital signal into an analog signal, a subtractor for calculating a difference between the signal output from the DAC and an analog signal input from a first Sample and Hold Amplifier (SHA), an amplifier for amplifying the difference, a first capacitor unit connected with an output end of the first SHA and an input end of the amplifier through a first switching unit, a second capacitor unit connected with the input end and an output end of the amplifier through a second switching unit, and a third capacitor unit connected with the input end and the output end of the amplifier through a third switching unit.
摘要翻译：提供了一种算法模数转换方法和算法模数转换器（ADC）。该算法ADC包括一个乘法数字模拟转换器（MDAC）。 MDAC包括用于将第一数字信号转换为模拟信号的数模转换器（DAC），减法器，用于计算从DAC输出的信号与从第一采样和保持放大器输入的模拟信号之间的差值 SHA），用于放大差分的放大器，通过第一开关单元与第一SHA的输出端连接的第一电容器单元和放大器的输入端，与输入端连接的第二电容器单元和输出端通过第二开关单元的放大器，以及通过第三开关单元与放大器的输入端和输出端连接的第三电容器单元。

5. 发明申请

US20080136699A1 ALGORITHM ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：算术模拟数字转换器
公开(公告)号：US20080136699A1
公开(公告)日：2008-06-12
申请号：US11946583
申请日：2007-11-28
申请人： Seung Chul LEE , Young Deuk JEON , Kwi Dong KIM , Jong Kee KWON
发明人： Seung Chul LEE , Young Deuk JEON , Kwi Dong KIM , Jong Kee KWON
IPC分类号： H03M1/38
CPC分类号： H03M1/0678 , H03M1/162
摘要： Provided is an algorithm analog-to-digital converter (ADC). The algorithm ADC obtains two digital outputs through different capacitor connections for one analog input signal and adds the digital output signals to obtain a final output value, so that a mismatch factor of the capacitor is removed to minimize a linearity limitation resulting from the capacitor mismatch. In addition, the algorithm ADC minimizes power consumption by making the operating frequency slow at a cycle requiring a high resolution and making the operating frequency fast at a cycle requiring a low resolution, i.e., outputting different operating clock frequencies according to a required resolution.
摘要翻译：提供了一种算法模数转换器（ADC）。算法ADC通过不同的电容器连接获得两个数字输出，用于一个模拟输入信号，并将数字输出信号相加以获得最终输出值，从而消除电容器的失配因子，以最小化由电容器失配引起的线性限制。此外，算法ADC通过使工作频率在需要高分辨率的周期中变慢，并使工作频率在需要低分辨率的周期（即，根据所需分辨率输出不同的工作时钟频率）的情况下将功率消耗最小化。

6. 发明申请

US20110140940A1 COEFFICIENT MULTIPLIER AND DIGITAL DELTA-SIGMA MODULATOR USING THE SAME 有权
标题翻译：使用相同的系数乘法器和数字三角形调制器
公开(公告)号：US20110140940A1
公开(公告)日：2011-06-16
申请号：US12783294
申请日：2010-05-19
申请人： Min Hyung CHO , Yi Gyeong KIM , Jong Kee KWON
发明人： Min Hyung CHO , Yi Gyeong KIM , Jong Kee KWON
IPC分类号： H03M3/00 , G06G7/28
CPC分类号： H03M7/3004 , H03M7/3033 , H03M7/304
摘要： Provided are a coefficient multiplier and digital delta-sigma modulator using the same. The coefficient multiplier has the average of output signals of respective dependent multipliers as an effective coefficient using a coefficient averaging technique without employing an adder that has a complex structure and occupies a large chip area. Accordingly, the coefficient multiplier has a simple hardware constitution and small chip area in comparison with a canonical signed digit (CSD) coefficient multiplier, and the digital delta-sigma modulator employing the coefficient multiplier has a simple structure and small size.
摘要翻译：提供了使用其的系数乘法器和数字Δ-Σ调制器。系数乘法器使用系数平均技术将各自的相关乘法器的输出信号的平均值作为有效系数，而不使用具有复杂结构的加法器并占据较大的码片面积。因此，系数乘法器与典型有符号数（CSD）系数乘法器相比，具有简单的硬件结构和小的芯片面积，并且采用系数乘法器的数字Δ-Σ调制器结构简单，体积小。

7. 发明申请

US20130033241A1 DC-DC CONVERTER CAPABLE OF CONFIGURING TOPOLOGY 有权
标题翻译： DC-DC转换器，可配置拓扑
公开(公告)号：US20130033241A1
公开(公告)日：2013-02-07
申请号：US13541108
申请日：2012-07-03
申请人： Sewan HEO , Yil Suk YANG , Jong Kee KWON
发明人： Sewan HEO , Yil Suk YANG , Jong Kee KWON
IPC分类号： G05F1/00
CPC分类号： H02M3/1582
摘要： Disclosed is a DC-DC converter including: a switch unit controlling a flow of a current based on a buck-boost topology; a short circuit unit short circuited or opened according to an external setting to change a topology of the switch unit; an inductor storing a current induced by the switch unit; a topology selecting unit selecting a topology in response to an external input signal and generating a signal corresponding to the selected topology; a pulse width modulating unit generating a signal for determining an operation time of the switch unit; a reverse flow detecting unit detecting a reverse flow of a current flowing through the switch unit to generate a signal; and a switch control unit controlling the switch unit in response to signals of the topology selecting unit, the pulse width modulating unit and the reverse flow detecting unit.
摘要翻译：公开了一种DC-DC转换器，包括：开关单元，其控制基于降压 - 升压拓扑的电流; 短路单元根据外部设置短路或断开，以改变开关单元的拓扑; 存储由所述开关单元感应的电流的电感器; 拓扑选择单元响应于外部输入信号选择拓扑并产生对应于所选拓扑的信号; 脉冲宽度调制单元，生成用于确定开关单元的操作时间的信号; 检测流过所述开关单元的电流的反向流以产生信号的逆流检测单元; 以及开关控制单元，其响应于拓扑选择单元，脉冲宽度调制单元和反向流检测单元的信号来控制开关单元。

8. 发明申请

US20110025537A1 ACTIVE RESISTANCE-CAPACITOR INTEGRATOR AND CONTINUOUS-TIME SIGMA-DELTA MODULATOR WITH GAIN CONTROL FUNCTION 有权
标题翻译：具有增益控制功能的主动电阻电容器积分器和连续时间信号调制器
公开(公告)号：US20110025537A1
公开(公告)日：2011-02-03
申请号：US12843591
申请日：2010-07-26
申请人： Yi Gyeong KIM , Min Hyung CHO , Jong Kee KWON
发明人： Yi Gyeong KIM , Min Hyung CHO , Jong Kee KWON
IPC分类号： H03M3/00 , G06G7/18
CPC分类号： G06G7/186 , H03M3/43 , H03M3/454 , H03M3/486
摘要： Provided are an active resistance-capacitance (RC) integrator and a continuous-time sigma-delta modulator, which have a gain control function. The active RC integrator includes an amplifier, a first base resistor connected between a first input node and a positive input port of the amplifier, a second base resistor connected between a second input node and a negative input port of the amplifier, a first resistor unit connected between the second input node and the positive input port of the amplifier, and a second resistor unit connected between the first input node and the negative input port of the amplifier. A resistor network including resistors and switches is configured to vary an input resistance, so that an active RC integrator may have a gain control function.
摘要翻译：提供了具有增益控制功能的有源电阻 - 电容（RC）积分器和连续时间Σ-Δ调制器。有源RC积分器包括放大器，连接在放大器的第一输入节点和正输入端口之间的第一基极电阻器，连接在放大器的第二输入节点和负输入端口之间的第二基极电阻器，第一电阻器单元连接在放大器的第二输入节点和正输入端口之间，以及连接在放大器的第一输入节点和负输入端口之间的第二电阻器单元。包括电阻器和开关的电阻器网络被配置为改变输入电阻，使得有源RC积分器可以具有增益控制功能。

9. 发明申请

US20100156534A1 GAIN CONTROL DEVICE AND AMPLIFIER USING THE SAME 有权
标题翻译：增益控制装置和使用它的放大器
公开(公告)号：US20100156534A1
公开(公告)日：2010-06-24
申请号：US12507701
申请日：2009-07-22
申请人： Yi Gyeong KIM , Min Hyung CHO , Jong Kee KWON
发明人： Yi Gyeong KIM , Min Hyung CHO , Jong Kee KWON
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F2203/45528 , H03F2203/45591
摘要： Provided are a gain control device and an amplifier using the gain control device. The gain control device includes a first input resistance unit having a first variable resistor whose resistance is linearly variable and a first fixed resistor respectively receiving a first input signal and a second input signal having a sign different from the first input signal and outputting current through a first output terminal, and a second input resistance unit having a second fixed resistor and a second variable resistor whose resistance is linearly variable respectively receiving the first input signal and the second input signal and outputting current through a second output terminal.Since the gain control device can separately perform dB-linear gain control, it is easily combined with a circuit, such as a continuous-time sigma-delta modulator (SDM), a continuous-time filter, and a continuous-time analog-to-digital converter (ADC), and enables miniaturization and low power consumption.
摘要翻译：提供了增益控制装置和使用增益控制装置的放大器。所述增益控制装置包括具有电阻为线性变化的第一可变电阻器和分别接收第一输入信号的第一固定电阻器和具有与第一输入信号不同的符号的第二输入信号的第一输入电阻单元，第一输出端子和具有第二固定电阻器和第二可变电阻器的第二输入电阻单元，其电阻为线性变化，分别接收第一输入信号和第二输入信号，并通过第二输出端子输出电流。由于增益控制装置可以单独执行dB线性增益控制，所以可以容易地与诸如连续时间Σ-Δ调制器（SDM），连续时间滤波器以及连续时间模拟到数字转换器（ADC），并实现小型化和低功耗。

10. 发明申请

US20100090756A1 SWITCHED CAPACITOR CIRCUIT WITH REDUCED LEAKAGE CURRENT 失效
标题翻译：具有降低漏电流的开关电容器电路
公开(公告)号：US20100090756A1
公开(公告)日：2010-04-15
申请号：US12469632
申请日：2009-05-20
申请人： Hyung Dong ROH , Hyoung Joong KIM , Jeong Jin ROH , Yi Gyeong KIM , Jong Kee KWON
发明人： Hyung Dong ROH , Hyoung Joong KIM , Jeong Jin ROH , Yi Gyeong KIM , Jong Kee KWON
IPC分类号： G05F1/10
CPC分类号： H03H19/004
摘要： Provided is a switched capacitor circuit which prevents leakage current by equalizing voltages at nodes where leakage current tends to flow in a sampling mode, and prevents errors in an output signal by minimizing voltage drop caused by leakage current in an integrating mode.
摘要翻译：提供一种开关电容器电路，其通过使漏电流趋于在采样模式中流动的节点处的电压相等来防止泄漏电流，并且通过使积分模式中的漏电流引起的电压降最小化来防止输出信号中的错误。

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