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1. 发明授权

US08547081B2 Reference voltage supply circuit including a glitch remover 有权
标题翻译：参考电压电路包括毛刺去除器
公开(公告)号：US08547081B2
公开(公告)日：2013-10-01
申请号：US12833841
申请日：2010-07-09
申请人： Young Deuk Jeon , Young Kyun Cho , Jae Won Nam , Jong Kee Kwon
发明人： Young Deuk Jeon , Young Kyun Cho , Jae Won Nam , Jong Kee Kwon
IPC分类号： G05F1/00 , G05F3/16 , G05F3/20
CPC分类号： H03F3/347
摘要： A reference voltage supply circuit is provided. The reference voltage supply circuit includes a first amplifier for amplifying a first input voltage and a fed back first reference voltage, a second amplifier for amplifying a second input voltage and a fed back second reference voltage, a reference voltage generator for generating the first reference voltage and the second reference voltage according to output signals of the first and second amplifiers and feeding the first and second reference voltages back to the first and second amplifiers, and a glitch remover turned on/off according to an input pulse signal to conduct or cut off current flowing between a power supply terminal and the ground.
摘要翻译：提供参考电压供应电路。参考电压供应电路包括用于放大第一输入电压和反馈第一参考电压的第一放大器，用于放大第二输入电压的第二放大器和反馈的第二参考电压;参考电压发生器，用于产生第一参考电压以及根据第一和第二放大器的输出信号的第二参考电压，并将第一和第二参考电压馈送回第一和第二放大器，并且毛刺去除器根据输入脉冲信号导通/截止以导通或切断在电源端子和地之间流动的电流。

2. 发明授权

US08264268B2 Offset-voltage calibration circuit 失效
标题翻译：偏置电压校准电路
公开(公告)号：US08264268B2
公开(公告)日：2012-09-11
申请号：US12843535
申请日：2010-07-26
申请人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
发明人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
IPC分类号： H03L5/00
CPC分类号： H03M1/1023 , H03M1/66
摘要： Provided is an offset-voltage calibration circuit. The circuit includes a comparator configured to receive at least two comparison voltages and output a result of a comparison between the comparison voltages, an up/down counter (UDC) configured to output an up-counting or down-counting output signal in response to an output signal of the comparator, and a current digital-to-analog converter (DAC) configured to control the amount of current supplied from a node to which the comparison voltage is applied, in response to the output signal of the UDC and control the magnitude of the comparison voltage.
摘要翻译：提供了一种偏移电压校准电路。所述电路包括比较器，被配置为接收至少两个比较电压并输出所述比较电压之间的比较结果;响应于所述比较电压被配置为输出递增计数或递减计数输出信号的上/下计数器（UDC）比较器的输出信号，以及被配置为响应于UDC的输出信号来控制从施加了比较电压的节点提供的电流量的电流数模转换器（DAC），并且控制幅度的比较电压。

3. 发明授权

US08059022B2 Digital-to-analog converter 有权
标题翻译：数模转换器
公开(公告)号：US08059022B2
公开(公告)日：2011-11-15
申请号：US12773768
申请日：2010-05-04
申请人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
发明人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
IPC分类号： H03M1/66
CPC分类号： H03M1/0682 , H03M1/468 , H03M1/68 , H03M1/682 , H03M1/804 , H03M1/806
摘要： A digital-to-analog converter (DAC) is provided. The DAC includes a positive converter, a negative converter, and a comparator for receiving outputs of the positive converter and the negative converter, comparing the outputs with a reference voltage, and generating an output voltage. Each of the positive converter and the negative converter includes an upper-bit converter including a plurality of bit capacitors corresponding to respective upper bits, a lower-bit converter including a plurality of bit capacitors corresponding to respective lower bits, and a coupling capacitor for connecting the upper-bit converter with the lower-bit converter in series. Each of the positive converter and the negative converter receives a bias voltage to have a uniform offset when converting the respective bits. Accordingly, it is possible to obtain a high resolution using a small area. Also, the number of capacitors can be reduced, and the capacitance of a unit capacitor can be maximized. Consequently, it is possible to minimize heat noise and device mismatching.
摘要翻译：提供了数模转换器（DAC）。 DAC包括正转换器，负转换器和用于接收正转换器和负转换器的输出的比较器，将输出与参考电压进行比较，并产生输出电压。正转换器和负转换器中的每个包括具有对应于各高位的多个位电容器的高位转换器，包括对应于各低位的多个位电容器的低位转换器和用于连接的耦合电容器低位转换器与低位转换器串联。正转换器和负转换器中的每一个在转换各个位时接收偏置电压以具有均匀的偏移。因此，可以使用小面积获得高分辨率。此外，可以减少电容器的数量，并且可以使单位电容器的电容最大化。因此，可以最小化热噪声和器件不匹配。

4. 发明授权

US08058863B2 Band-gap reference voltage generator 有权
标题翻译：带隙基准电压发生器
公开(公告)号：US08058863B2
公开(公告)日：2011-11-15
申请号：US12428425
申请日：2009-04-22
申请人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , JongKee Kwon
发明人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , JongKee Kwon
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： A band-gap reference voltage generator is provided. N-channel metal oxide semiconductor (NMOS) transistors are respectively connected to bipolar transistors in parallel. A Complementary To Absolute Temperature (CTAT) voltage that is inversely proportional to absolute temperature is reduced by a threshold voltage of the NMOS transistor. A weight for a temperature coefficient of a Proportional To Absolute Temperature (PTAT) voltage that is directly proportional to absolute temperature is reduced and a resistance ratio for a temperature coefficient of 0 is reduced by about ½, thereby miniaturizing the band-gap reference voltage generator. A reference voltage lower than or equal to 1 V can be provided by resistors respectively connected to the bipolar transistors in parallel.
摘要翻译：提供带隙参考电压发生器。 N沟道金属氧化物半导体（NMOS）晶体管分别并联连接到双极晶体管。与绝对温度成反比的绝对温度互补（CTAT）电压降低了NMOS晶体管的阈值电压。与绝对温度成正比的比例绝对温度（PTAT）电压的温度系数的重量减小，温度系数为0的电阻比减小约1/2，从而使带隙基准电压发生器。可以通过并联连接到双极晶体管的电阻器提供低于或等于1V的参考电压。

5. 发明申请

US20110121886A1 CLOCK DETECTOR AND BIAS CURRENT CONTROL CIRCUIT 审中-公开
标题翻译：时钟检测器和偏置电流控制电路
公开(公告)号：US20110121886A1
公开(公告)日：2011-05-26
申请号：US12859982
申请日：2010-08-20
申请人： Young Deuk JEON
发明人： Young Deuk JEON
IPC分类号： G11C5/14 , H03M1/50
CPC分类号： G06F1/32 , H03K5/19
摘要： Provided are a clock detector and a bias current control circuit. The clock detector outputs a digital code corresponding to the frequency of an input clock, and the bias current control circuit controls a bias current supplied to an analog circuit according to the digital code output from the clock detector. Accordingly, when the clock detector and the bias current control circuit are used, it is possible to minimize the power consumption of an analog circuit by controlling a bias current supplied to an analog circuit according to a digital code corresponding to the frequency of an input clock.
摘要翻译：提供了时钟检测器和偏置电流控制电路。时钟检测器输出对应于输入时钟的频率的数字码，并且偏置电流控制电路根据从时钟检测器输出的数字码来控制提供给模拟电路的偏置电流。因此，当使用时钟检测器和偏置电流控制电路时，可以通过根据对应于输入时钟的频率的数字代码来控制提供给模拟电路的偏置电流来最小化模拟电路的功耗。

6. 发明申请

US20110102220A1 PIPELINE ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：管道模拟数字转换器
公开(公告)号：US20110102220A1
公开(公告)日：2011-05-05
申请号：US12777910
申请日：2010-05-11
申请人： Jae Won NAM , Young Deuk Jeon , Young Kyun Cho , Jong Kee Kwon
发明人： Jae Won NAM , Young Deuk Jeon , Young Kyun Cho , Jong Kee Kwon
IPC分类号： H03M1/00 , H03M1/38
CPC分类号： H03M1/0836 , H03M1/168
摘要： Provided is a pipeline analog-to-digital converter (ADC) without a front-end sample-and-hold amplifier (SHA). To minimize a sampling error occurring between a flash ADC and a multiplying digital-to-analog converter (MDAC) of a first sub-ranging ADC due to removal of a front-end SHA, a delay time of a preamplifier included in the flash ADC is calculated, and the flash ADC samples an analog input signal later by the delay time than the MDAC. Accordingly, the pipeline ADC can minimize a sampling error without using a front-end SHA, and its chip area and power consumption can be reduced.
摘要翻译：提供了一种没有前端采样和保持放大器（SHA）的流水线模数转换器（ADC）。为了最小化由于去除前端SHA而导致的闪存ADC和第一子范围ADC的乘法数模转换器（MDAC）之间的采样误差，包括在闪存ADC中的前置放大器的延迟时间并且闪速ADC比模拟输入信号稍后采样延迟时间比MDAC。因此，流水线ADC可以在不使用前端SHA的情况下最小化采样误差，并且可以减少其芯片面积和功耗。

7. 发明申请

US20110018605A1 OFFSET-VOLTAGE CALIBRATION CIRCUIT 失效
标题翻译：偏移校准电路
公开(公告)号：US20110018605A1
公开(公告)日：2011-01-27
申请号：US12843535
申请日：2010-07-26
申请人： Young Kyun CHO , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
发明人： Young Kyun CHO , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
IPC分类号： H03L5/00
CPC分类号： H03M1/1023 , H03M1/66
摘要： Provided is an offset-voltage calibration circuit. The circuit includes a comparator configured to receive at least two comparison voltages and output a result of a comparison between the comparison voltages, an up/down counter (UDC) configured to output an up-counting or down-counting output signal in response to an output signal of the comparator, and a current digital-to-analog converter (DAC) configured to control the amount of current supplied from a node to which the comparison voltage is applied, in response to the output signal of the UDC and control the magnitude of the comparison voltage.
摘要翻译：提供了一种偏移电压校准电路。所述电路包括比较器，被配置为接收至少两个比较电压并输出所述比较电压之间的比较结果;响应于所述比较电压被配置为输出递增计数或递减计数输出信号的上/下计数器（UDC）比较器的输出信号，以及被配置为响应于UDC的输出信号来控制从施加了比较电压的节点提供的电流量的电流数模转换器（DAC），并且控制幅度的比较电压。

8. 发明申请

US20100123611A1 SUCCESSIVE APPROXIMATION REGISTER ANALOG-DIGITAL CONVERTER AND METHOD OF DRIVING THE SAME 有权
标题翻译：连续逼近寄存器模拟数字转换器及其驱动方法
公开(公告)号：US20100123611A1
公开(公告)日：2010-05-20
申请号：US12472375
申请日：2009-05-27
申请人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
发明人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
IPC分类号： H03M1/12
CPC分类号： H03M1/069 , H03M1/0607 , H03M1/468 , H03M1/804
摘要： A successive approximation register (SAR) analog-digital converter (ADC) and a method of driving the same are provided. The SAR ADC includes a first converting unit including a bit capacitor array corresponding to the number of bits and a correction capacitor array, a comparator outputting a high or low voltage corresponding to each capacitor according to an output voltage of the converting unit, and a correction unit correcting the output of the bit capacitor according to the output of the correction capacitor array among the high or low output of the comparator. Therefore, two bits having the same capacitance as a least significant bit (LSB) enable a digital output error to be corrected, so that a spurious free dynamic range (SFDR) of the signal converter is increased, and a signal to noise and distortion ratio (SNDR) of an output signal is improved.
摘要翻译：提供逐次逼近寄存器（SAR）模数转换器（ADC）及其驱动方法。 SAR ADC包括：第一转换单元，包括与位数相对应的位电容阵列和校正电容器阵列;比较器，根据转换单元的输出电压输出对应于每个电容器的高电压或低电压;以及校正单元根据比较器的高或低输出中的校正电容器阵列的输出校正位电容器的输出。因此，具有与最低有效位（LSB）相同的电容的两个位使得能够校正数字输出误差，使得信号转换器的无杂散动态范围（SFDR）增加，并且信噪比和失真比（SNDR）的输出信号得到改善。

9. 发明授权

US07683706B2 Gain amplifier having switched-capacitor structure for minimizing settling time 失效
标题翻译：具有开关电容器结构的增益放大器，用于最小化建立时间
公开(公告)号：US07683706B2
公开(公告)日：2010-03-23
申请号：US12195202
申请日：2008-08-20
申请人： Young Deuk Jeon , Young Kyun Cho , Kwi Dong Kim , Jong Kee Kwon , Jong Dae Kim
发明人： Young Deuk Jeon , Young Kyun Cho , Kwi Dong Kim , Jong Kee Kwon , Jong Dae Kim
IPC分类号： H03F1/02
CPC分类号： H03F3/005
摘要： Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized.
摘要翻译：提供一种增益放大器，其具有能够最小化建立时间的开关电容器结构，其中输入电容器在第一时钟对输入信号进行采样期间连接到输入端子，因此放大器的输出端子预先复位到输入电容器的估计输出电压值而不是0。因此，放大器的输出端子的轻微移动足以在放大模式下稳定到期望值，从而可以减少回转时间，结果可以使整体建立时间和功耗最小化。

10. 发明申请

US20090096646A1 METHOD OF ALGORITHMIC ANALOG-TO-DIGITAL CONVERSION AND ALGORITHMIC ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：算法模拟数字转换和算法模数转换器的方法
公开(公告)号：US20090096646A1
公开(公告)日：2009-04-16
申请号：US12198837
申请日：2008-08-26
申请人： Seung Chul LEE , Jae Won NAM , Young Deuk JEON , Jong Kee KWON
发明人： Seung Chul LEE , Jae Won NAM , Young Deuk JEON , Jong Kee KWON
IPC分类号： H03M1/12
CPC分类号： H03M1/1225 , H03M1/167
摘要： Provided are a method of algorithmic analog-to-digital conversion and an algorithmic Analog-to-Digital Converter (ADC). The algorithmic ADC includes a Multiplying Digital-to-Analog Converter (MDAC). The MDAC includes a Digital-to-Analog Converter (DAC) for converting a first digital signal into an analog signal, a subtractor for calculating a difference between the signal output from the DAC and an analog signal input from a first Sample and Hold Amplifier (SHA), an amplifier for amplifying the difference, a first capacitor unit connected with an output end of the first SHA and an input end of the amplifier through a first switching unit, a second capacitor unit connected with the input end and an output end of the amplifier through a second switching unit, and a third capacitor unit connected with the input end and the output end of the amplifier through a third switching unit.
摘要翻译：提供了一种算法模数转换方法和算法模数转换器（ADC）。该算法ADC包括一个乘法数字模拟转换器（MDAC）。 MDAC包括用于将第一数字信号转换为模拟信号的数模转换器（DAC），减法器，用于计算从DAC输出的信号与从第一采样和保持放大器输入的模拟信号之间的差值 SHA），用于放大差分的放大器，通过第一开关单元与第一SHA的输出端连接的第一电容器单元和放大器的输入端，与输入端连接的第二电容器单元和输出端通过第二开关单元的放大器，以及通过第三开关单元与放大器的输入端和输出端连接的第三电容器单元。

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