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1. 发明授权

US07233204B2 Method of acquiring low distortion and high linear characteristic in triode-typed transconductor 失效
标题翻译：在三极管型跨导体中获取低失真和高线性特性的方法
公开(公告)号：US07233204B2
公开(公告)日：2007-06-19
申请号：US10902678
申请日：2004-07-28
申请人： Young Ho Kim , Cheon Soo Kim , Mun Yang Park
发明人： Young Ho Kim , Cheon Soo Kim , Mun Yang Park
IPC分类号： H03F3/45
CPC分类号： H03F1/3211 , H03F2200/331
摘要： Provided is a method of acquiring a high linear characteristic and a low distortion in a transconductor (operational transconductance amplifier), especially, in a triode region type transconductor among CMOS transconductors. A resistance is inserted in a source or a drain of an input triode transistor. The transconductor has a simple circuit structure, and has a large linear region, constant transconductance and low total harmonic distortion (THD) characteristic within an error region.
摘要翻译：提供了一种在跨导体（运算跨导放大器）中获得高线性特性和低失真的方法，特别是在CMOS跨导体中的三极管区域型跨导体中。电阻被插入到输入三极管晶体管的源极或漏极中。跨导体具有简单的电路结构，并且在误差区域内具有大的线性区域，恒定的跨导和低的总谐波失真（THD）特性。

2. 发明授权

US07626476B2 Multi-metal coplanar waveguide 有权
标题翻译：多金属共面波导
公开(公告)号：US07626476B2
公开(公告)日：2009-12-01
申请号：US11690219
申请日：2007-03-23
申请人： Cheon Soo Kim , Myung Shin Kwak , Seong Do Kim , Mun Yang Park , Hyun Kyu Yu , Hee Bum Jung
发明人： Cheon Soo Kim , Myung Shin Kwak , Seong Do Kim , Mun Yang Park , Hyun Kyu Yu , Hee Bum Jung
IPC分类号： H01P3/08
CPC分类号： H01P3/003
摘要： A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.
摘要翻译：提供了一种使用多层互连CMOS技术的共面波导CPW。在包括设置在基板上的层间绝缘体的CPW中，设置在层间绝缘体上的金属多层和最下层的接地线的接地线 - 信号线 - 由最上层金属层形成的接地线连接到最上层的地线，中间金属层被设计成逐渐增加或减小宽度或不均匀，以便使超高频率扩展的面积最大化，由此最小化CPW损耗并最大化慢波效应。结果，可以提高超高频电路的性能并使电路小型化。

3. 发明授权

US07956658B2 Digital lock detector and frequency synthesizer using the same 有权
标题翻译：数字锁定检测器和频率合成器使用相同
公开(公告)号：US07956658B2
公开(公告)日：2011-06-07
申请号：US12607395
申请日：2009-10-28
申请人： Ja Yol Lee , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/16 , H03L7/095 , H03L7/099 , H03L7/103 , H03L2207/50
摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
摘要翻译：提供了数字锁定检测器和使用该锁定检测器的频率合成器。数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

4. 发明申请

US20100271072A1 DIGITAL LOCK DETECTOR AND FREQUENCY SYNTHESIZER USING THE SAME 有权
标题翻译：使用数字锁定检测器和频率合成器
公开(公告)号：US20100271072A1
公开(公告)日：2010-10-28
申请号：US12607395
申请日：2009-10-28
申请人： Ja Yol LEE , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
发明人： Ja Yol LEE , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03K5/22 , H03B21/00
CPC分类号： H03L7/16 , H03L7/095 , H03L7/099 , H03L7/103 , H03L2207/50
摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
摘要翻译：提供了数字锁定检测器和使用该锁定检测器的频率合成器。数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

5. 发明授权

US06992366B2 Stacked variable inductor 有权
标题翻译：堆叠式可变电感
公开(公告)号：US06992366B2
公开(公告)日：2006-01-31
申请号：US10671637
申请日：2003-09-29
申请人： Cheon Soo Kim , Pil Jae Park , Mun Yang Park , Hyun Kyu Yu
发明人： Cheon Soo Kim , Pil Jae Park , Mun Yang Park , Hyun Kyu Yu
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L28/10 , H01F17/0013 , H01F21/12 , H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Disclosed is a stacked variable inductors manufactured by stacking M (M≧2) metal layers on a semiconductor substrate, and provides stacked variable inductors comprising, 1 to N inductors continuously connected in serial, wherein each of said inductors is formed on N (N≦M) metal layers that are different each other; first and second ports each connected to the highest positioned inductor and to the lowest positioned inductor among said 1 to N inductors; and at least one MOSFET, and wherein one terminal of at least one MOSFET is connected to one of the first and second ports, and the other one is connected to one of adjacent terminals connected in serial between 1 to N inductors.
摘要翻译：公开了一种通过在半导体衬底上堆叠M（M> = 2）金属层而制造的层叠可变电感器，并提供包括串联连续连接的1至N个电感器的堆叠可变电感器，其中每个所述电感器形成在N <= M）彼此不同的金属层; 所述1至N电感器中的第一和第二端口各自连接到最高位置的电感器和最低位置的电感器; 和至少一个MOSFET，并且其中至少一个MOSFET的一个端子连接到所述第一和第二端口中的一个，并且另一个连接到串联连接在1至N个电感器之间的相邻端子之一。

6. 发明授权

US08013641B1 Frequency synthesizer including a digital lock detector 有权
标题翻译：频率合成器包括数字锁定检测器
公开(公告)号：US08013641B1
公开(公告)日：2011-09-06
申请号：US13098332
申请日：2011-04-29
申请人： Ja Yol Lee , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03B21/00
CPC分类号： H03L7/16 , H03L7/095 , H03L7/099 , H03L7/103 , H03L2207/50
摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
摘要翻译：提供了数字锁定检测器和使用该锁定检测器的频率合成器。数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

7. 发明授权

US08031009B2 Frequency calibration loop circuit 失效
标题翻译：频率校准回路电路
公开(公告)号：US08031009B2
公开(公告)日：2011-10-04
申请号：US12581105
申请日：2009-10-16
申请人： Byung Hun Min , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
发明人： Byung Hun Min , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03L7/085 , H03L7/095 , H03L7/18 , H03L7/081
CPC分类号： H03L7/181 , H03L2207/50 , Y10S331/02
摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.
摘要翻译：一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数）包括：振荡器，根据控制值调整振荡信号的振荡频率; 可编程分频器，根据分频比除以振荡信号，输出分频信号; 计数针对参考信号的一个周期的分频信号的时钟数，以输出计数值; 以及频率检测器，通过从参考比较值中减去计数值来获得控制值，其中通过将频率通道字（FCW）指令值除以可编程分频器的最小分频比来获得参考比较值。

8. 发明授权

US09508973B2 Secondary battery 有权
标题翻译：二次电池
公开(公告)号：US09508973B2
公开(公告)日：2016-11-29
申请号：US12633738
申请日：2009-12-08
申请人： Cheon Soo Kim
发明人： Cheon Soo Kim
IPC分类号： H01M4/02 , H01M2/16 , H01M2/22 , H01M4/13 , H01M10/04 , H01M10/0587 , H01M10/42 , H01M2/34 , H01M10/052
CPC分类号： H01M2/16 , H01M2/166 , H01M2/22 , H01M2/34 , H01M4/13 , H01M10/0436 , H01M10/052 , H01M10/0587 , H01M10/4235 , H01M2004/027 , Y02E60/122
摘要： An electrode assembly for a secondary battery comprising an adiabatic layer attached to the negative electrode layer is disclosed. The electrode assembly comprises a positive electrode layer having a positive electrode collector, a positive electrode coating, and a non-coated area on the positive electrode collector. The negative electrode layer has a negative electrode collector, a negative electrode coating, and a non-coated area on the negative electrode collector. A separator insulates the positive and negative electrode layers. Positive and negative electrode tabs are attached to the non-coated areas of the positive and negative electrode collectors. The negative electrode layer has an adiabatic layer attached to the surface of a non-coated area of the negative electrode collector that is opposite the surface to which the negative electrode tab is attached. This construction improves battery stability and prevents short circuits caused either by heat generated during overcharging or by an internal short circuit.
摘要翻译：公开了一种用于二次电池的电极组件，其包括连接到负极层的绝热层。电极组件包括在正极集电体上具有正极集电体，正电极涂层和未涂覆区域的正电极层。负极层在负极集电体上具有负极集电体，负极涂层和未涂覆区域。分离器绝缘正极层和负极层。正极和负极接线片连接到正极和负极集电器的未涂覆区域。负极层具有绝缘层，该绝热层附着在与负电极接头连接的表面相对的负极集电体的未涂覆区域的表面上。这种结构提高了电池的稳定性，并且防止由于过充电期间产生的热或内部短路引起的短路。

9. 发明授权

US09040202B2 Composite material tape for lithium secondary battery and lithium secondary battery using the same 有权
标题翻译：锂二次电池复合材料胶带和使用该锂二次电池的锂二次电池
公开(公告)号：US09040202B2
公开(公告)日：2015-05-26
申请号：US13402652
申请日：2012-02-22
申请人： Cheon Soo Kim , Hong Sup Lim , Sang Won Lee
发明人： Cheon Soo Kim , Hong Sup Lim , Sang Won Lee
IPC分类号： H01M2/16 , H01M4/13 , H01M4/72 , H01M2/08 , C09J7/02 , H01M2/02 , H01M2/10 , H01M2/32 , H01M10/052 , H01M10/0587 , H01M10/42 , C08K3/20 , C08K3/28 , H01M2/34
CPC分类号： H01M2/08 , C08K3/20 , C08K3/28 , C09J7/22 , C09J2205/106 , C09J2423/006 , C09J2467/006 , C09J2471/006 , C09J2479/086 , C09J2481/006 , H01M2/0275 , H01M2/1022 , H01M2/32 , H01M2/34 , H01M10/052 , H01M10/0587 , H01M10/425 , H01M2200/00 , Y02E60/122
摘要： A composite material tape and a lithium secondary battery using the same are provided. The composite material tape includes an organic base and at least one inorganic element dispersed within the organic base. The composite material tapes of the present invention exhibit improved Insulative and heat-resistant characteristics.
摘要翻译：提供复合材料带和使用其的锂二次电池。复合材料带包括有机基底和分散在有机基底内的至少一种无机元素。本发明的复合材料带表现出改善的绝缘和耐热特性。

10. 发明授权

US09013347B2 Radar apparatus 有权
标题翻译：雷达装置
公开(公告)号：US09013347B2
公开(公告)日：2015-04-21
申请号：US13445102
申请日：2012-04-12
申请人： Pil Jae Park , Cheon Soo Kim , Hyun Kyu Yu , Min Park , Ik Soo Eo
发明人： Pil Jae Park , Cheon Soo Kim , Hyun Kyu Yu , Min Park , Ik Soo Eo
IPC分类号： G01S13/74 , G01S13/08 , G01S13/58 , G01S13/32 , G01S7/00
CPC分类号： G01S13/325 , G01S7/003 , G01S13/584
摘要： An embodiment of the present invention relates to a radar apparatus, wherein a distance to a target and a velocity of the target are measured by transmitting a digitally modulated transmitting signal using a digital code and receiving and demodulating an echo signal returned due to reflection of the transmitting signal from the target.
摘要翻译：本发明的实施例涉及一种雷达装置，其中通过使用数字码发送数字调制的发射信号来测量与目标的距离和目标的速度，并且接收和解调由于反射而返回的回波信号从目标传输信号。

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