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1. 发明授权

US08193842B2 Frequency synthesizer 有权
公开(公告)号：US08193842B2
公开(公告)日：2012-06-05
申请号：US13344513
申请日：2012-01-05
申请人： Byung Hun Min , Hyun Kyu Yu
发明人： Byung Hun Min , Hyun Kyu Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/091 , H03L7/085 , H03L7/107 , H03L7/1075 , H03L7/183 , H03L2207/06 , H03L2207/50
摘要： There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency.

2. 发明申请

US20110150138A1 HIGH LINEARITY MIXER AND DIRECT CONVERSION RECEIVER USING THE SAME 审中-公开
标题翻译：高线性混合器和直接转换接收器
公开(公告)号：US20110150138A1
公开(公告)日：2011-06-23
申请号：US12970899
申请日：2010-12-16
申请人： Jung Woo PARK , Young Jae Lee , Hyun Kyu Yu , Byung Hun Min , Seong Do Kim , Hoai Nam Nguyen , Sang Gug Lee
发明人： Jung Woo PARK , Young Jae Lee , Hyun Kyu Yu , Byung Hun Min , Seong Do Kim , Hoai Nam Nguyen , Sang Gug Lee
IPC分类号： H03K9/00
CPC分类号： H04L25/08 , H03D7/1441 , H03D7/1458 , H03H19/004
摘要： A direct conversion receiver includes: a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit receiving an output signal from the sampler unit while having a low input impedance, amplifying the received signal, and outputting a current signal; and a filter device decimating an output signal from the mixer device and FIR-filtering the decimated signal.
摘要翻译：直接转换接收机包括：高线性混频器装置，包括：采样单元，根据采样频率对输入电流进行采样;以及缓冲单元，其具有低输入阻抗，从采样器单元接收输出信号，放大接收信号，并输出电流信号; 以及滤波器装置对来自混频器装置的输出信号进行抽取，并对抽取的信号进行FIR滤波。

3. 发明申请

US20100134192A1 FREQUENCY CALIBRATION LOOP CIRCUIT 失效
标题翻译：频率校准环路
公开(公告)号：US20100134192A1
公开(公告)日：2010-06-03
申请号：US12581105
申请日：2009-10-16
申请人： Byung Hun MIN , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
发明人： Byung Hun MIN , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03L7/00
CPC分类号： H03L7/181 , H03L2207/50 , Y10S331/02
摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting a oscillation frequency according to control value; a programmable divider dividing the oscillation frequency according to a division ratio; a counter counting the number of clocks of the divided frequency by using a reference frequency; and a frequency detector outputting a value obtained by subtracting the number of the counted clocks from a reference comparison value, a value obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider, as the control value of the oscillator.
摘要翻译：一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数）包括：振荡器根据控制值调节振荡频率; 一个可编程除法器根据分频比划分振荡频率; 通过使用参考频率对分频频率的时钟数进行计数的计数器; 输出通过从参考比较值中减去计数时钟数而得到的值的频率检测器，通过将频率通道字（FCW）指令值除以可编程分压器的最小分频比而获得的值作为控制值的振荡器。

4. 发明授权

US08258832B2 Loop filter and phase locked loop including the same 有权
标题翻译：环路滤波器和锁相环包括相同的
公开(公告)号：US08258832B2
公开(公告)日：2012-09-04
申请号：US12860498
申请日：2010-08-20
申请人： Byung Hun Min
发明人： Byung Hun Min
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03L7/093
摘要： Provided is a loop filter which receives first and second currents whose current ratio is n (where n is a natural number). The loop filter includes a first-order filter path, a second-order filter path, and a third-order filter path. The first-order filter path includes an operational amplifier generating an output impedance by increasing by as much as n times an impedance of a second input node to which the second current is applied. The first-order filter path performs a first-order filtering on the first current applied to a first input node by using the operational amplifier. The second-order filter path performs a second-order filtering on the first current applied to the first input node. The third-order filter path performs a third-order filtering on the first current applied to the first input node.
摘要翻译：提供一种环路滤波器，其接收电流比为n（其中n为自然数）的第一和第二电流。环路滤波器包括一阶滤波器路径，二阶滤波器路径和三阶滤波器路径。一阶滤波器路径包括运算放大器，通过将施加第二电流的第二输入节点的阻抗增加多达n倍，产生输出阻抗。一阶滤波器路径通过使用运算放大器对施加到第一输入节点的第一电流执行一阶滤波。二阶滤波器路径对施加到第一输入节点的第一电流执行二阶滤波。三阶滤波器路径对施加到第一输入节点的第一电流执行三阶滤波。

5. 发明申请

US20120105116A1 FREQUENCY SYNTHESIZER 有权
标题翻译：频率合成器
公开(公告)号：US20120105116A1
公开(公告)日：2012-05-03
申请号：US13344513
申请日：2012-01-05
申请人： Byung Hun MIN , Hyun Kyu Yu
发明人： Byung Hun MIN , Hyun Kyu Yu
IPC分类号： H03L7/08
CPC分类号： H03L7/091 , H03L7/085 , H03L7/107 , H03L7/1075 , H03L7/183 , H03L2207/06 , H03L2207/50
摘要： There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency.
摘要翻译：提供了一个频率合成器。频率合成器包括：频率振荡器，其根据控制位调整输出频率; 具有预设的最小分频比的可编程分频器，所述编程分频器以可分分频比划分所述频率振荡器的输出频率; 接收可编程分频器的输出信号的计数器单元和参考频率，以在参考频率的一个周期期间对可编程分频器的输出信号的上升沿进行计数以产生计数值，并且当计数值是1，并且当计数值为2时输出第二命中信号; 以及相位检测单元，输出通过从从计数值和参考频率获得的锁定相位的分数误差中减去可编程分频器的输出信号的分数误差而获得的控制位。

6. 发明授权

US08031009B2 Frequency calibration loop circuit 失效
标题翻译：频率校准回路电路
公开(公告)号：US08031009B2
公开(公告)日：2011-10-04
申请号：US12581105
申请日：2009-10-16
申请人： Byung Hun Min , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
发明人： Byung Hun Min , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03L7/085 , H03L7/095 , H03L7/18 , H03L7/081
CPC分类号： H03L7/181 , H03L2207/50 , Y10S331/02
摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.
摘要翻译：一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数）包括：振荡器，根据控制值调整振荡信号的振荡频率; 可编程分频器，根据分频比除以振荡信号，输出分频信号; 计数针对参考信号的一个周期的分频信号的时钟数，以输出计数值; 以及频率检测器，通过从参考比较值中减去计数值来获得控制值，其中通过将频率通道字（FCW）指令值除以可编程分频器的最小分频比来获得参考比较值。

7. 发明申请

US20110115535A1 LOOP FILTER AND PHASE LOCKED LOOP INCLUDING THE SAME 有权
标题翻译：环路滤波器和相位锁定环路，包括它们
公开(公告)号：US20110115535A1
公开(公告)日：2011-05-19
申请号：US12860498
申请日：2010-08-20
申请人： Byung Hun MIN
发明人： Byung Hun MIN
IPC分类号： H03L7/08 , H03K5/145
CPC分类号： H03L7/0893 , H03L7/093
摘要： Provided is a loop filter which receives first and second currents whose current ratio is n (where n is a natural number). The loop filter includes a first-order filter path, a second-order filter path, and a third-order filter path. The first-order filter path includes an operational amplifier generating an output impedance by increasing by as much as n times an impedance of a second input node to which the second current is applied. The first-order filter path performs a first-order filtering on the first current applied to a first input node by using the operational amplifier. The second-order filter path performs a second-order filtering on the first current applied to the first input node. The third-order filter path performs a third-order filtering on the first current applied to the first input node.
摘要翻译：提供一种环路滤波器，其接收电流比为n（其中n为自然数）的第一和第二电流。环路滤波器包括一阶滤波器路径，二阶滤波器路径和三阶滤波器路径。一阶滤波器路径包括运算放大器，通过将施加第二电流的第二输入节点的阻抗增加多达n倍，产生输出阻抗。一阶滤波器路径通过使用运算放大器对施加到第一输入节点的第一电流执行一阶滤波。二阶滤波器路径对施加到第一输入节点的第一电流执行二阶滤波。三阶滤波器路径对施加到第一输入节点的第一电流执行三阶滤波。

8. 发明申请

US20100134195A1 CAPACITOR HAVING VARIABLE CAPACITANCE AND DIGITALLY CONTROLLED OSCILLATOR INCLUDING THE SAME 审中-公开
标题翻译：具有可变电容的电容器和包括其的数字控制振荡器
公开(公告)号：US20100134195A1
公开(公告)日：2010-06-03
申请号：US12629742
申请日：2009-12-02
申请人： Ja Yol LEE , Byung Hun Min , Seong Do Kim , Hyun Kyu Yu
发明人： Ja Yol LEE , Byung Hun Min , Seong Do Kim , Hyun Kyu Yu
IPC分类号： H03B5/12 , H01L27/06
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1265
摘要： There is provided a capacitor having variable capacitance, which forms different capacitances according to a control signal by applying a switch to a metal-oxide-metal (MOM) structure plate capacitor using a CMOS process. The capacitor includes a stack structure including a plurality of metal layers including a first metal layer, and a plurality of dielectric layers respectively interposed between the plurality of metal layers, and a switch part including at least one switch having one side connected to at least one metal layer among the plurality of metal layers other than the first metal layer. The first metal layer and the other side of the switch serve as both terminals of the capacitor, and at least two capacitances are provided between both terminals of the capacitor upon controlling a short/open of the switch.
摘要翻译：提供具有可变电容的电容器，其通过使用CMOS工艺将开关施加到金属氧化物金属（MOM）结构板电容器上，根据控制信号形成不同的电容。电容器包括堆叠结构，其包括多个金属层，包括第一金属层和分别介于多个金属层之间的多个电介质层，以及开关部分，其包括至少一个开关，该开关的一侧连接至至少一个除了第一金属层之外的多个金属层中的金属层。开关的第一金属层和另一侧用作电容器的两端，并且在控制开关的短路/断开时，至少两个电容设置在电容器的两个端子之间。

9. 发明申请

US20100134160A1 FREQUENCY SYNTHESIZER 有权
标题翻译：频率合成器
公开(公告)号：US20100134160A1
公开(公告)日：2010-06-03
申请号：US12626554
申请日：2009-11-25
申请人： Byung Hun MIN , Hyun Kyu YU
发明人： Byung Hun MIN , Hyun Kyu YU
IPC分类号： H03L7/08
CPC分类号： H03L7/091 , H03L7/085 , H03L7/107 , H03L7/1075 , H03L7/183 , H03L2207/06 , H03L2207/50
摘要： There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency.
摘要翻译：提供了一个频率合成器。频率合成器包括根据控制位调节输出频率的频率振荡器; 具有预设的最小分频比的可编程分频器，所述编程分频器以可分分频比划分所述频率振荡器的输出频率; 接收可编程分频器的输出信号的计数器单元和参考频率，以在参考频率的一个周期期间对可编程分频器的输出信号的上升沿进行计数以产生计数值，并且当计数值是1，并且当计数值为2时输出第二命中信号; 以及相位检测单元，输出通过从从计数值和参考频率获得的锁定相位的分数误差中减去可编程分频器的输出信号的分数误差而获得的控制位。

10. 发明授权

US07675374B2 Voltage controlled oscillator with switching bias 有权
标题翻译：具有开关偏压的压控振荡器
公开(公告)号：US07675374B2
公开(公告)日：2010-03-09
申请号：US12111555
申请日：2008-04-29
申请人： Byung Hun Min , Young Ho Kim , Byoung Gun Choi , Seok Bong Hyun
发明人： Byung Hun Min , Young Ho Kim , Byoung Gun Choi , Seok Bong Hyun
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03B5/04 , H03B5/1215 , H03B5/1228 , H03B5/1243
摘要： Provided is a voltage controlled oscillator to which a switching bias technique is applied so as to lower flicker noise of a bias circuit and enhance phase noise characteristics, thereby reducing the overall chip area to make it possible to achieve integration. A common mode voltage applied to the bias circuit is negatively fed back to an oscillation waveform. Therefore, it is possible to stabilize the magnitude of the oscillation waveform of the voltage controlled oscillator with respect to a change in an external condition.
摘要翻译：提供了一种施加了开关偏压技术的压控振荡器，以便降低偏置电路的闪烁噪声并增强相位噪声特性，由此减小整个芯片面积以实现集成。施加到偏置电路的共模电压被反馈回振荡波形。因此，可以相对于外部条件的变化来稳定压控振荡器的振荡波形的大小。

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