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1. 发明授权

US5830805A Electroless deposition equipment or apparatus and method of performing electroless deposition 失效
标题翻译：无电沉积设备或进行无电沉积的设备和方法
公开(公告)号：US5830805A
公开(公告)日：1998-11-03
申请号：US751631
申请日：1996-11-18
申请人： Yosi Shacham-Diamand , Valery M. Dubin , Chiu H. Ting , Bin Zhao , Prahalad K. Vasudev
发明人： Yosi Shacham-Diamand , Valery M. Dubin , Chiu H. Ting , Bin Zhao , Prahalad K. Vasudev
IPC分类号： C23C18/16 , H01L21/288 , H01L21/44
CPC分类号： C23C18/1683 , H01L21/288 , C23C18/1619 , Y10S438/908 , Y10S438/913
摘要： An electroless deposition apparatus and a method of electroless deposition that uses a single process chamber for performing multiple processes by moving through the process chamber a variety of fluids one at a time in a sequential order.
摘要翻译：一种无电沉积装置和无电沉积方法，其使用单个处理室通过以顺序顺序一次一个地通过处理室移动各种流体来执行多个处理。

2. 发明授权

US5824599A Protected encapsulation of catalytic layer for electroless copper interconnect 失效
标题翻译：用于无电铜互连的催化层的保护封装
公开(公告)号：US5824599A
公开(公告)日：1998-10-20
申请号：US587264
申请日：1996-01-16
申请人： Yosef Schacham-Diamand , Valery M. Dubin , Chiu H. Ting , Bin Zhao , Prahalad K. Vasudev , Melvin Desilva
发明人： Yosef Schacham-Diamand , Valery M. Dubin , Chiu H. Ting , Bin Zhao , Prahalad K. Vasudev , Melvin Desilva
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76874 , H01L21/76858 , Y10S977/712 , Y10S977/81 , Y10S977/888 , Y10S977/89
摘要： A method for utilizing electroless copper deposition to form interconnects on a semiconductor. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum over the barrier layer. Next, without breaking the vacuum, an aluminum protective layer is deposited onto the catalytic layer to encapsulate and protect the catalytic layer from oxidizing. An electroless deposition technique is then used to auto-catalytically deposit copper on the catalytic layer. The electroless deposition solution dissolves the overlying protective layer to expose the surface of the underlying catalytic layer. The electroless copper deposition occurs on this catalytic surface, and continues until the via/trench is filled. Subsequently, the copper and barrier material are polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) barrier layer and the overlying SiN layer.
摘要翻译：一种利用无电铜沉积在半导体上形成互连的方法。一旦在电介质层中形成通孔或沟槽，则沉积氮化钛（TiN）或钽（Ta）阻挡层。然后，催化铜籽晶层在真空中在阻挡层上共形地覆盖。接下来，在不破坏真空的情况下，将铝保护层沉积到催化剂层上以包封并保护催化剂层免于氧化。然后使用无电沉积技术在催化剂层上自动催化沉积铜。无电沉积溶液溶解上覆的保护层以暴露下面的催化剂层的表面。无电铜沉积发生在该催化剂表面上，并持续直到通孔/沟槽被填充。随后，通过施加化学机械抛光（CMP）来抛光铜和阻挡材料，以从表面去除多余的铜和阻挡材料，使得剩余的唯一的铜和阻挡材料在通孔/沟槽开口中。然后，在暴露的铜上方形成覆盖氮化硅（SiN）层，以形成电介质阻挡层。铜互连通过TiN（或Ta）阻挡层和覆盖的SiN层从相邻材料完全封装。

3. 发明授权

US5695810A Use of cobalt tungsten phosphide as a barrier material for copper metallization 失效
标题翻译：使用磷钨酸钴作为铜金属化的阻挡材料
公开(公告)号：US5695810A
公开(公告)日：1997-12-09
申请号：US754600
申请日：1996-11-20
申请人： Valery M. Dubin , Yosi Schacham-Diamand , Bin Zhao , Prahalad K. Vasudev , Chiu H. Ting
发明人： Valery M. Dubin , Yosi Schacham-Diamand , Bin Zhao , Prahalad K. Vasudev , Chiu H. Ting
IPC分类号： C23C18/16 , C23C18/50 , H01L21/768 , B05D5/12 , B05D1/18
CPC分类号： H01L21/76831 , C23C18/1603 , C23C18/1651 , C23C18/1689 , C23C18/405 , C23C18/50 , H01L21/288 , H01L21/76843 , H01L21/76849 , H01L21/76876 , H01L21/76879 , H01L2221/1089
摘要： A technique for electrolessly depositing a CoWP barrier material on to copper and electrolessly depositing copper onto a CoWP barrier material to prevent copper diffusion when forming layers and/or structures on a semiconductor wafer.
摘要翻译：一种用于将CoWP阻挡材料无电沉积到铜上并在CoWP阻挡材料上无电沉积铜以防止在半导体晶片上形成层和/或结构时铜扩散的技术。

4. 发明授权

US5674787A Selective electroless copper deposited interconnect plugs for ULSI applications 失效
标题翻译：用于ULSI应用的选择性无电铜沉积互连插头
公开(公告)号：US5674787A
公开(公告)日：1997-10-07
申请号：US587263
申请日：1996-01-16
申请人： Bin Zhao , Prahalad K. Vasudev , Valery M. Dubin , Yosef Shacham-Diamand , Chiu H. Ting
发明人： Bin Zhao , Prahalad K. Vasudev , Valery M. Dubin , Yosef Shacham-Diamand , Chiu H. Ting
IPC分类号： H01L21/288 , H01L21/768 , H01L21/28
CPC分类号： H01L21/76831 , H01L21/288 , H01L21/76849 , H01L21/76874 , H01L21/76879 , Y10S977/81
摘要： A method or utilizing electroless copper deposition to selectively form encapsulated copper plugs to connect conductive regions on a semiconductor. A via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD. Once the underlying metal layer is exposed by the via opening, a SiN or SiON dielectric encapsulation layer is formed along the sidewalls of the via. Then, a contact displacement technique is used to form a thin activation layer of copper on a barrier metal, such as TiN, which is present as a covering layer on the underlying metal layer. After the contact displacement of copper on the barrier layer at the bottom of the via, an electroless copper deposition technique is then used to auto-catalytically deposit copper in the via. The electroless copper deposition continues until the via is almost filled, but leaving sufficient room at the top in order to form an upper encapsulation layer. The SiN or SiON sidewalls, the bottom barrier layer and the cap barrier layer function to fully encapsulate the copper plug in the via. The plug is then annealed.
摘要翻译：一种方法或利用无电镀铜沉积来选择性地形成封装的铜塞以连接半导体上的导电区域。层间电介质（ILD）中的通孔开口提供用于连接由ILD分离的两个导电区域的路径。一旦底层金属层被通孔开口暴露，沿通孔的侧壁形成SiN或SiON电介质封装层。然后，使用接触位移技术在阻挡金属上形成薄的铜活化层，例如在下面的金属层上作为覆盖层存在的TiN。在通孔底部的阻挡层上的铜的接触位移之后，然后使用无电解铜沉积技术自动催化将铜沉积在通孔中。无电铜沉积继续直到通孔几乎被填充，但是在顶部留下足够的空间以形成上封装层。 SiN或SiON侧壁，底部阻挡层和帽阻挡层用于将铜塞完全封装在通孔中。然后将塞子退火。

5. 发明授权

US5891513A Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications 失效
标题翻译：通过用于ULSI应用的CU接触位移，在阻挡层上沉积化学镀
公开(公告)号：US5891513A
公开(公告)日：1999-04-06
申请号：US587262
申请日：1996-01-16
申请人： Valery M. Dubin , Yosef Shacham-Diamand , Chiu H. Ting , Bin Zhao , Prahalad K. Vasudev
发明人： Valery M. Dubin , Yosef Shacham-Diamand , Chiu H. Ting , Bin Zhao , Prahalad K. Vasudev
IPC分类号： C23C18/16 , H01L21/288 , H01L21/768 , H01L23/532 , H05K3/04 , H05K3/38 , H05K3/42 , H05K3/46 , B05D5/12
CPC分类号： H01L21/76843 , C23C18/1603 , C23C18/1651 , C23C18/1689 , C23C18/1831 , C23C18/1879 , C23C18/54 , H01L21/288 , H01L21/76807 , H01L21/76874 , H01L21/76877 , H01L23/53238 , H05K3/388 , H05K3/465 , H01L2924/0002 , H05K2201/09563 , H05K2203/072 , H05K2203/0733 , H05K3/045 , H05K3/422 , H05K3/4661 , Y10S977/892
摘要： A method of utilizing electroless copper deposition to form interconnects on a semiconductor wafer. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is blanket deposited. Then, a contact displacement technique is used to form a thin activation seed layer of copper on the barrier layer. An electroless deposition technique is then used to auto-catalytically deposit copper on the activated barrier layer. The electroless copper deposition continues until the via/trench is filled. Subsequently, the surface is polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) and the SiN layers.
摘要翻译：一种利用无电铜沉积在半导体晶片上形成互连的方法。一旦在电介质层中形成通孔或沟槽，则氮化钛（TiN）或钽（Ta）阻挡层被覆盖沉积。然后，使用接触位移技术在阻挡层上形成铜的薄的活化种子层。然后使用无电沉积技术在活化的阻挡层上自动催化沉积铜。继续进行化学镀铜沉积，直到通孔/沟槽被填充。随后，通过施加化学机械抛光（CMP）来抛光表面以从表面去除多余的铜和阻挡材料，使得剩余的唯一的铜和阻挡材料在通孔/沟槽开口中。然后，在暴露的铜上方形成覆盖氮化硅（SiN）层，以形成电介质阻挡层。铜互连通过TiN（或Ta）和SiN层从相邻材料完全封装。

6. 发明授权

US09085461B2 Method and apparatus to fabricate polymer arrays on patterned wafers using electrochemical synthesis 有权
标题翻译：使用电化学合成在图案化晶片上制造聚合物阵列的方法和装置
公开(公告)号：US09085461B2
公开(公告)日：2015-07-21
申请号：US13473338
申请日：2012-05-16
申请人： Valery M. Dubin , Florian Gstrein , Gordon D. Holt , Brandon Barnett
发明人： Valery M. Dubin , Florian Gstrein , Gordon D. Holt , Brandon Barnett
IPC分类号： H01L21/00 , B82Y30/00 , B01J19/00
CPC分类号： B82Y30/00 , B01J19/0046 , B01J2219/00497 , B01J2219/005 , B01J2219/00527 , B01J2219/00574 , B01J2219/00576 , B01J2219/00585 , B01J2219/00596 , B01J2219/00653 , B01J2219/00659 , B01J2219/00662 , B01J2219/00675 , B01J2219/00677 , B01J2219/00689 , B01J2219/00713 , B01J2219/00722 , B01J2219/00725
摘要： A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
摘要翻译：具有在晶片上具有多个管芯（也称为阵列芯片）的晶片，该管芯具有产生脱保护试剂的电极，用于电化学合成材料的工作电极，邻近工作电极的约束电极以限制反应性试剂，以及管芯焊盘，其中，所述多个管芯的管芯焊盘在晶片上互连，以在多个工作电极上并行地电化学地合成所述材料。另外，公开了一种用于晶片尺寸制造多个管芯的方法和用于在晶片上的多个管芯上并行地电化学合成材料的方法。

7. 发明授权

US08541876B2 Microelectronic package having direct contact heat spreader and method of manufacturing same 有权
标题翻译：具有直接接触式散热器的微电子封装及其制造方法
公开(公告)号：US08541876B2
公开(公告)日：2013-09-24
申请号：US11242176
申请日：2005-09-30
申请人： Daoqiang Lu , Chuan Hu , Gilroy J. Vandentop , Shriram Ramanathan , Rajashree Baskaran , Valery M. Dubin
发明人： Daoqiang Lu , Chuan Hu , Gilroy J. Vandentop , Shriram Ramanathan , Rajashree Baskaran , Valery M. Dubin
IPC分类号： H01L23/10
CPC分类号： H01L24/83 , H01L21/4871 , H01L23/3735 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/83 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/18161 , H01L2924/19106 , H01L2924/00
摘要： A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.
摘要翻译：一种制造具有直接接触散热器的微电子封装的方法，根据该方法形成的封装，根据该方法形成的模具散热器组合以及包含封装的系统。该方法包括金属化微电子管芯的背面以形成直接接触并固定到管芯背面的散热器主体，从而产生模具散热器组合。该封装包括模具散热器组合和与模具结合的衬底。

8. 发明授权

US08053774B2 Method and apparatus to fabricate polymer arrays on patterned wafers using electrochemical synthesis 有权
标题翻译：使用电化学合成在图案化晶片上制造聚合物阵列的方法和装置
公开(公告)号：US08053774B2
公开(公告)日：2011-11-08
申请号：US11144679
申请日：2005-06-06
申请人： Valery M. Dubin , Florian Gstrein , Gordon D. Holt , Brandon Barnett
发明人： Valery M. Dubin , Florian Gstrein , Gordon D. Holt , Brandon Barnett
IPC分类号： H01L23/58
CPC分类号： B82Y30/00 , B01J19/0046 , B01J2219/00497 , B01J2219/005 , B01J2219/00527 , B01J2219/00574 , B01J2219/00576 , B01J2219/00585 , B01J2219/00596 , B01J2219/00653 , B01J2219/00659 , B01J2219/00662 , B01J2219/00675 , B01J2219/00677 , B01J2219/00689 , B01J2219/00713 , B01J2219/00722 , B01J2219/00725
摘要： A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
摘要翻译：具有在晶片上具有多个管芯（也称为阵列芯片）的晶片，该管芯具有产生脱保护试剂的电极，用于电化学合成材料的工作电极，邻近工作电极的约束电极以限制反应性试剂，以及管芯焊盘，其中，所述多个管芯的管芯焊盘在晶片上互连，以在多个工作电极上并行地电化学地合成所述材料。另外，公开了一种用于晶片尺寸制造多个管芯的方法和用于在晶片上的多个管芯上并行地电化学合成材料的方法。

9. 发明授权

US07709873B2 Polymer memory with adhesion layer containing an immobilized metal 有权
标题翻译：含有固定金属的粘合层的聚合物记忆
公开(公告)号：US07709873B2
公开(公告)日：2010-05-04
申请号：US11096389
申请日：2005-03-31
申请人： Valery M. Dubin , Ebrahim Andideh
发明人： Valery M. Dubin , Ebrahim Andideh
IPC分类号： H01L29/76 , H01L29/74 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10 , B82Y10/00 , B82Y30/00 , H01L29/516 , H01L29/78391 , Y10T29/435
摘要： An embodiment mitigates one or more of the limiting factors of fabricating polymer ferroelectric memory devices. For example, an embodiment reduces the degradation of the ferroelectric polymer due to the polymer's reaction with, and migration or diffusion of, adjacent metal electrode material. Further, the ferroelectric polymer is exposed to fewer potentially high temperature or high energy processes that may damage the polymer. An embodiment further incorporates an immobilized catalyst to improve the adhesion between adjacent layers, and particularly between the electrolessly plated electrodes and the ferroelectric polymer.
摘要翻译：一个实施例减轻了制造聚合物铁电存储器件的一个或多个限制因素。例如，一个实施方案由于聚合物与相邻的金属电极材料的反应和迁移或扩散而降低了铁电聚合物的劣化。此外，铁电聚合物暴露于可能损坏聚合物的较少的潜在高温或高能量过程。一个实施方案还包括固定化的催化剂以改善相邻层之间的粘合性，特别是在无电镀电极和铁电聚合物之间。

10. 发明申请

US20100022083A1 CARBON NANOTUBE INTERCONNECT STRUCTURES 审中-公开
标题翻译：碳纳米管互连结构
公开(公告)号：US20100022083A1
公开(公告)日：2010-01-28
申请号：US12548779
申请日：2009-08-27
申请人： Florian Gstrein , Valery M. Dubin , Juan E. Dominguez , Adrien R. Lavoie
发明人： Florian Gstrein , Valery M. Dubin , Juan E. Dominguez , Adrien R. Lavoie
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/76838 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/75 , H01L2924/00
摘要： A method including forming an interconnect of single-walled carbon nanotubes on a sacrificial substrate; transferring the interconnect from the sacrificial substrate to a circuit substrate; and coupling the interconnect to a contact point on the circuit substrate. A method including forming a nanotube bundle on a circuit substrate between a first contact point and a second contact point, the nanotube defining a lumen therethrough; filling a portion of a length of the lumen of the nanotube bundle with an electrically conductive material; and coupling the electrically conductive material to the second contact point. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board, the microprocessor including a substrate having a plurality of circuit devices with electrical connections made to the plurality of circuit devices through interconnect structures including carbon nanotube bundles.
摘要翻译：一种包括在牺牲衬底上形成单层碳纳米管的互连的方法; 将所述互连件从所述牺牲衬底转移到电路衬底; 以及将所述互连件耦合到所述电路基板上的接触点。一种方法，包括在第一接触点和第二接触点之间的电路基板上形成纳米管束，所述纳米管限定通过其的腔; 用导电材料填充纳米管束管腔长度的一部分; 以及将所述导电材料耦合到所述第二接触点。一种包括计算设备的系统，包括微处理器，微处理器耦合到印刷电路板，微处理器包括具有多个电路器件的衬底，该电路器件具有通过包括碳纳米管束的互连结构与多个电路器件形成的电连接。

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