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1. 发明授权

US5027177A Floating base lateral bipolar phototransistor with field effect gate voltage control 失效
标题翻译：浮动基极横向双极光电晶体管，具有场效应栅极电压控制
公开(公告)号：US5027177A
公开(公告)日：1991-06-25
申请号：US383469
申请日：1989-07-24
申请人： Prahalad K. Vasudev
发明人： Prahalad K. Vasudev
IPC分类号： H01L27/144 , H01L29/73 , H01L29/739 , H01L29/786 , H01L31/11 , H01L31/113
CPC分类号： H01L29/78648 , H01L27/1443 , H01L29/7317 , H01L29/7394 , H01L31/1105 , H01L31/113
摘要： A lateral bipolar phototransistor having a floating, photosensitive base region is formed in a silicon layer on an insulator substrate. Insulated gate electrodes are formed above and below the base reigon and are voltage biased to create a field effect causing majority carriers to accumulate in the base region. The majority carriers accumulate in layers which face the respective gate electrodes and extend between an emitter and collector of the bipolar transistor. A bias voltage applied to the gate electrodes has a polarity opposite to a polarity of the majority carriers in the emitter and collector regions and is sufficiently high to bias field effect transistors constituted by the gate electrodes in combination with the emitter, base and collector of the bipolar phototransistor into cutoff. The accumulation creates a depleted base region with reduced parasitic capacitance and resistance, thereby enabling higher frequency operation and current gain.
摘要翻译：具有浮动感光基区的横向双极光电晶体管形成在绝缘体基板上的硅层中。绝缘栅电极形成在基极上方和下方，并且被电压偏压以产生场效应，导致多数载流子积累在基极区中。多数载流子以面对各个栅电极并在双极晶体管的发射极和集电极之间延伸的层累积。施加到栅电极的偏置电压具有与发射极和集电极区域中的多数载流子的极性相反的极性，并且足够高以将由栅电极构成的场效应晶体管与发射极，基极和集电极组合双极光电晶体管切断。累积产生具有降低的寄生电容和电阻的耗尽的基极区域，从而实现更高的频率操作和电流增益。

2. 发明授权

US4826300A Silicon-on-sapphire liquid crystal light valve and method 失效
标题翻译：硅蓝宝石液晶光阀和方法
公开(公告)号：US4826300A
公开(公告)日：1989-05-02
申请号：US79607
申请日：1987-07-30
申请人： Uzi Efron , Paul O. Braatz , Prahalad K. Vasudev , Glenn D. Robertson
发明人： Uzi Efron , Paul O. Braatz , Prahalad K. Vasudev , Glenn D. Robertson
IPC分类号： G02F1/135 , G02F1/13
CPC分类号： G02F1/1354
摘要： An LCLV is formed with a sapphire substrate base, a highly doped, thin silicon epitaxial layer forming an ohmic back contact on a smooth surface of the sapphire substrate, and a lightly doped, high resistivity silicon epitaxial layer in the range of about 20-60 microns thick on the back contact. The use of a sapphire substrate provides a better surface quality and higher resolution than previously available with the semiconductor substrates. Lattice defects in the thin back contact are reduced by the formation of a buried amorphous layer adjacent the sapphire substrate, and subsequent recrystallization thereof using the unamorphized portions of the back contact as recrystallization seeds. The application of the invention to both MOS and Schottky diode LCLVs is discussed.
摘要翻译： LCLV由在蓝宝石衬底的光滑表面上形成欧姆背接触的蓝宝石衬底基底，高度掺杂的薄硅外延层和轻掺杂的高电阻率硅外延层形成，其范围为约20-60 背面接触微米厚。使用蓝宝石衬底提供比以前可用的半导体衬底更好的表面质量和更高的分辨率。通过在蓝宝石衬底附近形成埋置的非晶层，减少薄背接触中的晶格缺陷，随后使用后接触的未变质部分再结晶作为再结晶种子。讨论了将本发明应用于MOS和肖特基二极管LCLV。

3. 发明授权

US4816893A Low leakage CMOS/insulator substrate devices and method of forming the same 失效
标题翻译：低泄漏CMOS /绝缘体衬底器件及其形成方法
公开(公告)号：US4816893A
公开(公告)日：1989-03-28
申请号：US166145
申请日：1988-03-10
申请人： Donald C. Mayer , Prahalad K. Vasudev
发明人： Donald C. Mayer , Prahalad K. Vasudev
IPC分类号： H01L21/20 , H01L21/86 , H01L27/02
CPC分类号： H01L21/86 , H01L21/0242 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02667 , H01L21/02694
摘要： A method of fabricating CMOS circuit devices on an insulator substrate is disclosed in which a solid phase epitaxy process is applied to islands for the individual devices in the same step as the channel dopant implants. An ion species, preferably silicon for a silicon island, is implanted into each island at an energy and dosage sufficient to amorphize a buried layer of the island in the vicinity of an underlying insulated substrate; silicon-on-sapphire (SOS) is preferably employed. The buried layers are then recrystallized, using the unamorphized portions of the semiconducotr islands as crystallization seeds. Islands of generally uniform, high quality semiconductor material are thus obtained which utilize dopant implants more efficiently, and avoid prior parasitic transistors and leakage currents. By implanting the ion species to a greater depth than the nominal island thickness for n-channel devices, and to a lesser depth than the nominal island thickness for p-channel devices, back channel current leakage is reduced while undesirable aluminum auto doping is avoided for the p-channel devices.
摘要翻译：公开了一种在绝缘体衬底上制造CMOS电路器件的方法，其中在与沟道掺杂剂注入相同的步骤中，将固相外延工艺应用于各个器件的岛。将离子种类，优选用于硅岛的硅，以足够的能量和剂量注入每个岛中，以使下层绝缘基底附近的岛的掩埋层非晶化; 硅蓝宝石（SOS）优选使用。然后将埋层重结晶，使用半导体岛的未变形部分作为结晶种子。因此获得了更均匀，高质量的半导体材料的岛，其更有效地利用掺杂剂注入，并且避免了先前的寄生晶体管和漏电流。通过将离子种类植入到比n沟道器件的标称岛厚度更深的深度上，并且对于p沟道器件的深度小于标称岛厚度，反向沟道电流泄漏减少，避免了不期望的铝自动掺杂 p通道设备。

4. 发明授权

US4659392A Selective area double epitaxial process for fabricating silicon-on-insulator structures for use with MOS devices and integrated circuits 失效
标题翻译：用于制造用于MOS器件和集成电路的绝缘体上硅结构的选择性区域双外延工艺
公开(公告)号：US4659392A
公开(公告)日：1987-04-21
申请号：US890449
申请日：1986-07-30
申请人： Prahalad K. Vasudev
发明人： Prahalad K. Vasudev
IPC分类号： H01L21/20 , H01L21/265 , H01L21/86 , H01L21/263 , H01L21/225
CPC分类号： H01L21/86 , H01L21/0242 , H01L21/02433 , H01L21/02532 , H01L21/02694 , H01L21/26506 , Y10S148/077
摘要： A process is disclosed for preparing selectively doped and recrystallized silicon-on-insulator semiconductor wafers, and wafers prepared thereby, wherein successive amorphizing and annealing sequences are utilized to optimize the defect structure and doping of multiple regions or islands of the silicon on an insulator substrate. Prior to fabrication of the active devices, the various silicon islands are given customized ion implantation treatments to amorphize a silicon near-interface layer under differing sets of implantation conditions. The entire wafer is then annealed to achieve downward epitaxial recrystallization of the amorphized near-interface layers in all of the amorphized islands, growing on the near-surface crystalline layer of the silicon remote from the interface. The near-surface layers of the islands are then amorphized and annealed to achieve upward epitaxial recrystallization of the layers on the underlying silicon layer. By this approach, the crystalline defect structure and the dopant distributions of the islands are individually optimized for specific applications.
摘要翻译：公开了一种用于制备选择性掺杂和重结晶硅绝缘体上半导体晶片以及由此制备的晶片的方法，其中使用连续的非晶化和退火序列来优化缺陷结构和在绝缘体衬底上掺杂多个硅的岛的区域。在制造有源器件之前，给予各种硅岛以定制的离子注入处理，以在不同的植入条件下对硅近界层进行非晶化。然后将整个晶片退火以实现所有非晶化岛中的非晶化近界面层的向下外延重结晶，生长在远离界面的硅的近表面结晶层上。然后将岛的近表面层非晶化并退火，以实现下层硅层上的层的向上外延重结晶。通过这种方法，岛的结晶缺陷结构和掺杂剂分布针对特定应用单独优化。

5. 发明授权

US4617066A Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing 失效
标题翻译：通过注入和两步退火制备具有浅的，高度突变的掺杂区的半导体的工艺
公开(公告)号：US4617066A
公开(公告)日：1986-10-14
申请号：US674623
申请日：1984-11-26
申请人： Prahalad K. Vasudev
发明人： Prahalad K. Vasudev
IPC分类号： H01L21/20 , H01L21/265 , H01L21/324 , H01L21/263 , H01L21/225
CPC分类号： H01L21/324 , H01L21/0237 , H01L21/02381 , H01L21/0242 , H01L21/0245 , H01L21/02532 , H01L21/02573 , H01L21/02694 , H01L21/26506 , H01L21/26513 , H01L21/2652 , Y10S148/024 , Y10S148/061
摘要： A method for producing hyperabrupt P.+-. or N.+-. regions in a near-surface layer of a substantially defect free crystal, using solid phase epitaxy and transient annealing. The process for producing a hyperabrupt retrograde distribution of the dopant species begins with amorphizing the near-surface layer of a base crystal, and then implanting a steep retrograde distribution of the desired species into the amorphized layer, so that the retrograde distribution lies entirely within the amorphized layer, thereby avoiding channelling effects during implantation. The substantially defect-free structure of the base crystal is restored by annealing the implanted base crystal at a temperature sufficiently high to induce solid phase epitaxial regrowth on the underlying nonamorphized crystal, but at a temperature sufficiently low to avoid significant diffusion of the implanted species. The implanted species is subsequently activated by a rapid thermal annealing process, at a temperature sufficiently high to activate the implanted species, but for a very short time so that long-range diffusion does not occur. In a preferred embodiment, the implanted species is boron, BF.sub.2.sup.+, phosphorus, or arsenic in the top 0.20 micrometers of a substantially defect-free silicon base crystal, which may be in a bulk form or epitaxially deposited on an insulator substrate such as sapphire.
摘要翻译：使用固相外延和瞬态退火在基本无缺陷晶体的近表面层中产生超破坏的P +/-或N +/-区的方法。用于产生掺杂剂物质的超破坏逆向分布的方法开始于将基底的近表面层非晶化，然后将所需物质的陡峭逆向分布植入非晶化层中，使得逆行分布完全位于非晶化层，从而避免植入过程中的沟道效应。通过在足够高的温度下对植入的基底晶体退火以在下面的未变形晶体上引发固相外延再生长，但在足够低的温度下避免植入物质的显着扩散来恢复基本晶体的基本上无缺陷的结构。随后通过快速热退火工艺，在足够高的温度下活化植入的物种，但在非常短的时间内激活注入物种，使得不发生远程扩散。在一个优选的实施方案中，注入的物质是在基本上无缺陷的硅基晶体的顶部0.20微米内的硼，BF 2 +，磷或砷，其可以是体积形式或外延沉积在诸如蓝宝石的绝缘体衬底上。

6. 发明授权

US4509990A Solid phase epitaxy and regrowth process with controlled defect density profiling for heteroepitaxial semiconductor on insulator composite substrates 失效
标题翻译：固相外延和再生长过程与异质外延半导体绝缘体复合衬底的受控缺陷密度分布
公开(公告)号：US4509990A
公开(公告)日：1985-04-09
申请号：US441477
申请日：1982-11-15
申请人： Prahalad K. Vasudev
发明人： Prahalad K. Vasudev
IPC分类号： H01L21/20 , H01L21/265 , H01L21/324
CPC分类号： H01L21/02694 , H01L21/0242 , H01L21/02532 , H01L21/26506 , H01L21/2654 , H01L21/3245
摘要： Disclosed is a method of fabricating a semiconductor on insulator composite substrate comprised of a semiconductor layer adjacent an insulator substrate, the defect density profile of the semiconductor layer being low and relatively uniform, a relatively thin region of the semiconductor layer at the semiconductor/insulator interface having a substantially greater defect density. The method comprises the steps of depositing the semiconductor layer adjacent the insulator substrate, amorphizing a buried portion of the semiconductor layer without damaging the insulator substrate such as to release contaminants into the semiconductor layer, recrystallizing the amorphous portion of the semiconductor or layer, removing a portion of the semiconductor layer so as to expose the recrystallized layer, and depositing an additional semiconductor layer on the recrystallized layer to provide an essentially defect free semiconductor layer of any desired thickness. The provision of semiconductor layers formed by either appropriately selecting the depth within the semiconductor layer at which the amorphization occurs and the width of the amorphized region or permitting self-annealing to occur during the amorphization, or both, having a desired high defect density and interposed between the recrystallized layer and the insulator substrate are also disclosed.
摘要翻译：公开了一种制造绝缘体上半导体复合衬底的方法，该半导体复合衬底由邻近绝缘体衬底的半导体层组成，半导体层的缺陷密度分布低且相对均匀，在半导体/绝缘体界面处的半导体层的相对薄的区域具有显着更大的缺陷密度。该方法包括以下步骤：将半导体层沉积在绝缘体衬底附近，使半导体层的掩埋部分非晶化，而不会损坏绝缘体衬底，以便将污染物释放到半导体层中，使半导体或层的非晶部分重结晶，以暴露再结晶层，并在再结晶层上沉积另外的半导体层，以提供任何所需厚度的基本上无缺陷的半导体层。提供半导体层，通过适当选择发生非晶化的半导体层内的深度和非晶化区域的宽度或允许在非晶化期间发生的自退火或者两者具有期望的高缺陷密度而形成，并且插入还公开了再结晶层和绝缘体基板之间。

7. 发明授权

US5824599A Protected encapsulation of catalytic layer for electroless copper interconnect 失效
标题翻译：用于无电铜互连的催化层的保护封装
公开(公告)号：US5824599A
公开(公告)日：1998-10-20
申请号：US587264
申请日：1996-01-16
申请人： Yosef Schacham-Diamand , Valery M. Dubin , Chiu H. Ting , Bin Zhao , Prahalad K. Vasudev , Melvin Desilva
发明人： Yosef Schacham-Diamand , Valery M. Dubin , Chiu H. Ting , Bin Zhao , Prahalad K. Vasudev , Melvin Desilva
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76874 , H01L21/76858 , Y10S977/712 , Y10S977/81 , Y10S977/888 , Y10S977/89
摘要： A method for utilizing electroless copper deposition to form interconnects on a semiconductor. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum over the barrier layer. Next, without breaking the vacuum, an aluminum protective layer is deposited onto the catalytic layer to encapsulate and protect the catalytic layer from oxidizing. An electroless deposition technique is then used to auto-catalytically deposit copper on the catalytic layer. The electroless deposition solution dissolves the overlying protective layer to expose the surface of the underlying catalytic layer. The electroless copper deposition occurs on this catalytic surface, and continues until the via/trench is filled. Subsequently, the copper and barrier material are polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) barrier layer and the overlying SiN layer.
摘要翻译：一种利用无电铜沉积在半导体上形成互连的方法。一旦在电介质层中形成通孔或沟槽，则沉积氮化钛（TiN）或钽（Ta）阻挡层。然后，催化铜籽晶层在真空中在阻挡层上共形地覆盖。接下来，在不破坏真空的情况下，将铝保护层沉积到催化剂层上以包封并保护催化剂层免于氧化。然后使用无电沉积技术在催化剂层上自动催化沉积铜。无电沉积溶液溶解上覆的保护层以暴露下面的催化剂层的表面。无电铜沉积发生在该催化剂表面上，并持续直到通孔/沟槽被填充。随后，通过施加化学机械抛光（CMP）来抛光铜和阻挡材料，以从表面去除多余的铜和阻挡材料，使得剩余的唯一的铜和阻挡材料在通孔/沟槽开口中。然后，在暴露的铜上方形成覆盖氮化硅（SiN）层，以形成电介质阻挡层。铜互连通过TiN（或Ta）阻挡层和覆盖的SiN层从相邻材料完全封装。

8. 发明授权

US5695810A Use of cobalt tungsten phosphide as a barrier material for copper metallization 失效
标题翻译：使用磷钨酸钴作为铜金属化的阻挡材料
公开(公告)号：US5695810A
公开(公告)日：1997-12-09
申请号：US754600
申请日：1996-11-20
申请人： Valery M. Dubin , Yosi Schacham-Diamand , Bin Zhao , Prahalad K. Vasudev , Chiu H. Ting
发明人： Valery M. Dubin , Yosi Schacham-Diamand , Bin Zhao , Prahalad K. Vasudev , Chiu H. Ting
IPC分类号： C23C18/16 , C23C18/50 , H01L21/768 , B05D5/12 , B05D1/18
CPC分类号： H01L21/76831 , C23C18/1603 , C23C18/1651 , C23C18/1689 , C23C18/405 , C23C18/50 , H01L21/288 , H01L21/76843 , H01L21/76849 , H01L21/76876 , H01L21/76879 , H01L2221/1089
摘要： A technique for electrolessly depositing a CoWP barrier material on to copper and electrolessly depositing copper onto a CoWP barrier material to prevent copper diffusion when forming layers and/or structures on a semiconductor wafer.
摘要翻译：一种用于将CoWP阻挡材料无电沉积到铜上并在CoWP阻挡材料上无电沉积铜以防止在半导体晶片上形成层和/或结构时铜扩散的技术。

9. 发明授权

US5474865A Globally planarized binary optical mask using buried absorbers 失效
标题翻译：全局平面二值光掩模使用埋地吸收器
公开(公告)号：US5474865A
公开(公告)日：1995-12-12
申请号：US342940
申请日：1994-11-21
申请人： Prahalad K. Vasudev
发明人： Prahalad K. Vasudev
IPC分类号： G03F1/00 , G03F1/38 , G03F1/60 , G03F9/00
CPC分类号： G03F1/60 , G03F1/50
摘要： A globally planarized binary optical mask has absorbers embedded (buried) in the mask substrate, instead of on the surface of the mask. Light scattering at rough vertical edges of absorbers of prior art masks are reduced or eliminated. Also, due to the buried nature of the absorbers, a triple singularity point encountered in prior art masks at the interface of three environments of quartz, absorber and air, no longer exists. The buried absorbers have an offset distance from the surface of the substrate so that with a minimum effective offset distance, defects and contaminants at the surface of the mask are no longer in the image plane, wherein alleviating a need for a pellicle to protect the mask surface. By reducing light scattering and distortion, the mask of the present invention allows for conventional optical lithography to be extended to ranges of shorter wavelength.
摘要翻译：全局平面化二元光学掩模在掩模衬底中嵌入（掩埋）吸收体，而不是在掩模的表面上。现有技术的掩模的吸收体的粗糙垂直边缘处的光散射被减少或消除。此外，由于吸收体的埋藏性质，在现有技术中在石英，吸收体和空气的三种环境的界面处遇到的三重奇点不再存在。掩埋的吸收体与衬底的表面具有偏移距离，使得在最小的有效偏移距离处，掩模表面处的缺陷和污染物不再在图像平面中，其中减轻了对防护薄膜的保护的需要表面。通过减少光散射和变形，本发明的掩模允许将常规的光学光刻扩展到较短波长的范围。

10. 发明授权

US5472811A Phase shifting mask structure with multilayer optical coating for improved transmission 失效
标题翻译：具有多层光学涂层的相移掩模结构，用于改进透射
公开(公告)号：US5472811A
公开(公告)日：1995-12-05
申请号：US236870
申请日：1994-04-29
申请人： Prahalad K. Vasudev , Kah K. Low
发明人： Prahalad K. Vasudev , Kah K. Low
IPC分类号： G03F1/26 , G03F1/30 , G03F9/00
CPC分类号： G03F1/30 , G03F1/26 , Y10T428/24479
摘要： A multi-layer PSM structure with multi-layer optical coating disposed between a quartz substrate and a surrounding medium, which typically is air. The multi-layer coating is comprised of a high index of refraction material overlying the quartz and a lower index of refraction material overlying the first. The multi-layer coating essentially functions as an anti-reflective coating to reduce scattering and reflection at the interface boundaries.
摘要翻译：具有多层光学涂层的多层PSM结构，其设置在石英基板和通常为空气的周围介质之间。多层涂层由覆盖在石英上的高折射率材料和覆盖在第一层上的较低的折射率材料构成。多层涂层基本起到抗反射涂层的作用，以减少界面边界处的散射和反射。

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