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1. 发明授权

US5824599A Protected encapsulation of catalytic layer for electroless copper interconnect 失效
标题翻译：用于无电铜互连的催化层的保护封装
公开(公告)号：US5824599A
公开(公告)日：1998-10-20
申请号：US587264
申请日：1996-01-16
申请人： Yosef Schacham-Diamand , Valery M. Dubin , Chiu H. Ting , Bin Zhao , Prahalad K. Vasudev , Melvin Desilva
发明人： Yosef Schacham-Diamand , Valery M. Dubin , Chiu H. Ting , Bin Zhao , Prahalad K. Vasudev , Melvin Desilva
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76874 , H01L21/76858 , Y10S977/712 , Y10S977/81 , Y10S977/888 , Y10S977/89
摘要： A method for utilizing electroless copper deposition to form interconnects on a semiconductor. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum over the barrier layer. Next, without breaking the vacuum, an aluminum protective layer is deposited onto the catalytic layer to encapsulate and protect the catalytic layer from oxidizing. An electroless deposition technique is then used to auto-catalytically deposit copper on the catalytic layer. The electroless deposition solution dissolves the overlying protective layer to expose the surface of the underlying catalytic layer. The electroless copper deposition occurs on this catalytic surface, and continues until the via/trench is filled. Subsequently, the copper and barrier material are polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) barrier layer and the overlying SiN layer.
摘要翻译：一种利用无电铜沉积在半导体上形成互连的方法。一旦在电介质层中形成通孔或沟槽，则沉积氮化钛（TiN）或钽（Ta）阻挡层。然后，催化铜籽晶层在真空中在阻挡层上共形地覆盖。接下来，在不破坏真空的情况下，将铝保护层沉积到催化剂层上以包封并保护催化剂层免于氧化。然后使用无电沉积技术在催化剂层上自动催化沉积铜。无电沉积溶液溶解上覆的保护层以暴露下面的催化剂层的表面。无电铜沉积发生在该催化剂表面上，并持续直到通孔/沟槽被填充。随后，通过施加化学机械抛光（CMP）来抛光铜和阻挡材料，以从表面去除多余的铜和阻挡材料，使得剩余的唯一的铜和阻挡材料在通孔/沟槽开口中。然后，在暴露的铜上方形成覆盖氮化硅（SiN）层，以形成电介质阻挡层。铜互连通过TiN（或Ta）阻挡层和覆盖的SiN层从相邻材料完全封装。

2. 发明授权

US5891513A Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications 失效
标题翻译：通过用于ULSI应用的CU接触位移，在阻挡层上沉积化学镀
公开(公告)号：US5891513A
公开(公告)日：1999-04-06
申请号：US587262
申请日：1996-01-16
申请人： Valery M. Dubin , Yosef Shacham-Diamand , Chiu H. Ting , Bin Zhao , Prahalad K. Vasudev
发明人： Valery M. Dubin , Yosef Shacham-Diamand , Chiu H. Ting , Bin Zhao , Prahalad K. Vasudev
IPC分类号： C23C18/16 , H01L21/288 , H01L21/768 , H01L23/532 , H05K3/04 , H05K3/38 , H05K3/42 , H05K3/46 , B05D5/12
CPC分类号： H01L21/76843 , C23C18/1603 , C23C18/1651 , C23C18/1689 , C23C18/1831 , C23C18/1879 , C23C18/54 , H01L21/288 , H01L21/76807 , H01L21/76874 , H01L21/76877 , H01L23/53238 , H05K3/388 , H05K3/465 , H01L2924/0002 , H05K2201/09563 , H05K2203/072 , H05K2203/0733 , H05K3/045 , H05K3/422 , H05K3/4661 , Y10S977/892
摘要： A method of utilizing electroless copper deposition to form interconnects on a semiconductor wafer. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is blanket deposited. Then, a contact displacement technique is used to form a thin activation seed layer of copper on the barrier layer. An electroless deposition technique is then used to auto-catalytically deposit copper on the activated barrier layer. The electroless copper deposition continues until the via/trench is filled. Subsequently, the surface is polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) and the SiN layers.
摘要翻译：一种利用无电铜沉积在半导体晶片上形成互连的方法。一旦在电介质层中形成通孔或沟槽，则氮化钛（TiN）或钽（Ta）阻挡层被覆盖沉积。然后，使用接触位移技术在阻挡层上形成铜的薄的活化种子层。然后使用无电沉积技术在活化的阻挡层上自动催化沉积铜。继续进行化学镀铜沉积，直到通孔/沟槽被填充。随后，通过施加化学机械抛光（CMP）来抛光表面以从表面去除多余的铜和阻挡材料，使得剩余的唯一的铜和阻挡材料在通孔/沟槽开口中。然后，在暴露的铜上方形成覆盖氮化硅（SiN）层，以形成电介质阻挡层。铜互连通过TiN（或Ta）和SiN层从相邻材料完全封装。

3. 发明授权

US5830805A Electroless deposition equipment or apparatus and method of performing electroless deposition 失效
标题翻译：无电沉积设备或进行无电沉积的设备和方法
公开(公告)号：US5830805A
公开(公告)日：1998-11-03
申请号：US751631
申请日：1996-11-18
申请人： Yosi Shacham-Diamand , Valery M. Dubin , Chiu H. Ting , Bin Zhao , Prahalad K. Vasudev
发明人： Yosi Shacham-Diamand , Valery M. Dubin , Chiu H. Ting , Bin Zhao , Prahalad K. Vasudev
IPC分类号： C23C18/16 , H01L21/288 , H01L21/44
CPC分类号： C23C18/1683 , H01L21/288 , C23C18/1619 , Y10S438/908 , Y10S438/913
摘要： An electroless deposition apparatus and a method of electroless deposition that uses a single process chamber for performing multiple processes by moving through the process chamber a variety of fluids one at a time in a sequential order.
摘要翻译：一种无电沉积装置和无电沉积方法，其使用单个处理室通过以顺序顺序一次一个地通过处理室移动各种流体来执行多个处理。

4. 发明授权

US5695810A Use of cobalt tungsten phosphide as a barrier material for copper metallization 失效
标题翻译：使用磷钨酸钴作为铜金属化的阻挡材料
公开(公告)号：US5695810A
公开(公告)日：1997-12-09
申请号：US754600
申请日：1996-11-20
申请人： Valery M. Dubin , Yosi Schacham-Diamand , Bin Zhao , Prahalad K. Vasudev , Chiu H. Ting
发明人： Valery M. Dubin , Yosi Schacham-Diamand , Bin Zhao , Prahalad K. Vasudev , Chiu H. Ting
IPC分类号： C23C18/16 , C23C18/50 , H01L21/768 , B05D5/12 , B05D1/18
CPC分类号： H01L21/76831 , C23C18/1603 , C23C18/1651 , C23C18/1689 , C23C18/405 , C23C18/50 , H01L21/288 , H01L21/76843 , H01L21/76849 , H01L21/76876 , H01L21/76879 , H01L2221/1089
摘要： A technique for electrolessly depositing a CoWP barrier material on to copper and electrolessly depositing copper onto a CoWP barrier material to prevent copper diffusion when forming layers and/or structures on a semiconductor wafer.
摘要翻译：一种用于将CoWP阻挡材料无电沉积到铜上并在CoWP阻挡材料上无电沉积铜以防止在半导体晶片上形成层和/或结构时铜扩散的技术。

5. 发明授权

US5674787A Selective electroless copper deposited interconnect plugs for ULSI applications 失效
标题翻译：用于ULSI应用的选择性无电铜沉积互连插头
公开(公告)号：US5674787A
公开(公告)日：1997-10-07
申请号：US587263
申请日：1996-01-16
申请人： Bin Zhao , Prahalad K. Vasudev , Valery M. Dubin , Yosef Shacham-Diamand , Chiu H. Ting
发明人： Bin Zhao , Prahalad K. Vasudev , Valery M. Dubin , Yosef Shacham-Diamand , Chiu H. Ting
IPC分类号： H01L21/288 , H01L21/768 , H01L21/28
CPC分类号： H01L21/76831 , H01L21/288 , H01L21/76849 , H01L21/76874 , H01L21/76879 , Y10S977/81
摘要： A method or utilizing electroless copper deposition to selectively form encapsulated copper plugs to connect conductive regions on a semiconductor. A via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD. Once the underlying metal layer is exposed by the via opening, a SiN or SiON dielectric encapsulation layer is formed along the sidewalls of the via. Then, a contact displacement technique is used to form a thin activation layer of copper on a barrier metal, such as TiN, which is present as a covering layer on the underlying metal layer. After the contact displacement of copper on the barrier layer at the bottom of the via, an electroless copper deposition technique is then used to auto-catalytically deposit copper in the via. The electroless copper deposition continues until the via is almost filled, but leaving sufficient room at the top in order to form an upper encapsulation layer. The SiN or SiON sidewalls, the bottom barrier layer and the cap barrier layer function to fully encapsulate the copper plug in the via. The plug is then annealed.
摘要翻译：一种方法或利用无电镀铜沉积来选择性地形成封装的铜塞以连接半导体上的导电区域。层间电介质（ILD）中的通孔开口提供用于连接由ILD分离的两个导电区域的路径。一旦底层金属层被通孔开口暴露，沿通孔的侧壁形成SiN或SiON电介质封装层。然后，使用接触位移技术在阻挡金属上形成薄的铜活化层，例如在下面的金属层上作为覆盖层存在的TiN。在通孔底部的阻挡层上的铜的接触位移之后，然后使用无电解铜沉积技术自动催化将铜沉积在通孔中。无电铜沉积继续直到通孔几乎被填充，但是在顶部留下足够的空间以形成上封装层。 SiN或SiON侧壁，底部阻挡层和帽阻挡层用于将铜塞完全封装在通孔中。然后将塞子退火。

6. 发明授权

US6037664A Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer 失效
标题翻译：使用低介电常数材料的双层镶嵌互连结构用于层间电介质层
公开(公告)号：US6037664A
公开(公告)日：2000-03-14
申请号：US52215
申请日：1998-03-31
申请人： Bin Zhao , Prahalad K. Vasudev , Ronald S. Horwath , Thomas E. Seidel , Peter M. Zeitzoff
发明人： Bin Zhao , Prahalad K. Vasudev , Ronald S. Horwath , Thomas E. Seidel , Peter M. Zeitzoff
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76849 , H01L21/7681 , H01L21/76843 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , Y10S438/902
摘要： A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.epsilon.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which via and trench openings are formed in the low-.epsilon. ILD. The dual damascene technique allows for both the via and trench openings to be filled at the same time.
摘要翻译：一种使用低介电常数材料作为电介质层或多层制造双镶嵌互连结构的技术。使用低介电常数（低ε）电介质材料在金属化层之间形成层间介电层（ILD）层，其中在低εILD中形成通孔和沟槽开口。双镶嵌技术允许通孔和沟槽开口同时被填充。

7. 发明授权

US6100184A Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer 失效
标题翻译：使用低介电常数材料制造用于层间电介质层的双镶嵌互连结构的方法
公开(公告)号：US6100184A
公开(公告)日：2000-08-08
申请号：US914995
申请日：1997-08-20
申请人： Bin Zhao , Prahalad K. Vasudev , Ronald S. Horwath , Thomas E. Seidel , Peter M. Zeitzoff
发明人： Bin Zhao , Prahalad K. Vasudev , Ronald S. Horwath , Thomas E. Seidel , Peter M. Zeitzoff
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76849 , H01L21/7681 , H01L21/76843 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , Y10S438/902
摘要： A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.di-elect cons.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which via and trench openings are formed in the low-.di-elect cons. ILD. The dual damascene technique allows for both the via and trench openings to be filled at the same time.
摘要翻译：一种使用低介电常数材料作为电介质层或多层制造双镶嵌互连结构的技术。低介电常数（低+ 531）介电材料用于在金属化层之间形成层间电介质层（ILD）层，其中通孔和沟槽开口形成在低+ 531 ILD中。双镶嵌技术允许通孔和沟槽开口同时被填充。

8. 发明授权

US5660706A Electric field initiated electroless metal deposition 失效
标题翻译：电场引发无电金属沉积
公开(公告)号：US5660706A
公开(公告)日：1997-08-26
申请号：US688466
申请日：1996-07-30
申请人： Bin Zhao , Prahalad K. Vasudev
发明人： Bin Zhao , Prahalad K. Vasudev
IPC分类号： C23C18/16 , H01L21/288 , H01L21/768 , C25D5/02 , C25D5/04 , C25D7/12 , C25D17/00
CPC分类号： H01L21/76831 , C23C18/1607 , C23C18/1651 , C23C18/1653 , C23C18/1669 , C23C18/1671 , H01L21/2885 , H01L21/76805 , H01L21/76843 , H01L21/76874 , H01L21/76879
摘要： A technique for utilizing an electric field to initiate electroless deposition of a material to form layers and/or structures on a semiconductor wafer. The wafer is disposed between a positive electrode and a negative electrode and disposed so that its deposition surface faces the positive electrode. A conductive surface on the wafer is then subjected to an electroless copper deposition solution. When copper is the conductive material being deposited, positive copper ions in the solution are repelled by the positive electrode and attracted by the negatively charged wafer surface. Once physical contact is made, the copper ions dissipate their charges by accepting electrons from the conductive surface, thereby forming copper atoms on the surface. The deposited copper have the catalytic properties so that when a reductant in the solution is absorbed at the copper sites and then oxidized, additional electrons are released into the conductive surface. The formation of the initial layer of copper functions as a seed layer for further electroless growth of copper. The same electroless deposition solution can be used for both the initial activation layer and the additional autocatalytic growth on to the seed layer.
摘要翻译：一种利用电场来引发化学沉积材料以在半导体晶片上形成层和/或结构的技术。晶片设置在正电极和负电极之间并且被设置为使得其沉积表面面向正电极。然后将晶片上的导电表面经受化学镀铜沉积溶液。当铜是导电材料沉积时，溶液中的正铜离子被正极排斥并被带负电的晶片表面吸引。一旦进行物理接触，铜离子通过从导电表面接受电子而耗散它们的电荷，从而在表面上形成铜原子。沉积的铜具有催化性能，使得当溶液中的还原剂在铜位置被吸收然后被氧化时，附加的电子被释放到导电表面中。铜的初始层的形成用作用于铜的进一步无电生长的种子层。相同的无电沉积溶液可以用于初始活化层和在种子层上的额外的自催化生长。

9. 发明授权

US10212958B2 Method for producing stabilized whole wheat flour 有权
公开(公告)号：US10212958B2
公开(公告)日：2019-02-26
申请号：US14111679
申请日：2012-04-13
申请人： Bin Zhao , Ning Zhou , Timothy S. Hansen , Michael A. Duffin , Domenico R. Cassone , Diane L. Gannon , Lynn C. Haynes , James M. Manns , Jeanny E. Zimeri , Peter Worfolk , Anthony Pracek
发明人： Bin Zhao , Ning Zhou , Timothy S. Hansen , Michael A. Duffin , Domenico R. Cassone , Diane L. Gannon , Lynn C. Haynes , James M. Manns , Jeanny E. Zimeri , Peter Worfolk , Anthony Pracek
IPC分类号： A23L1/211 , A23L7/10 , A21D2/14 , A21D2/36 , A21D2/38 , A21D6/00 , A21D13/02 , B02B1/08
摘要： A stabilized flour, such as stabilized whole grain wheat flour, exhibiting unexpectedly superior extended shelf life and superior biscuit baking functionality, may be produced with or without heating to inhibit lipase by subjecting whole grains or a bran and germ fraction or component to treatment with a lipase inhibitor, such as an acid or green tea extract. Treatment with the lipase inhibitor may be performed during tempering of the whole grains or berries or during hydration of the bran and germ fraction or component.

10. 发明授权

US09749205B2 Systems and methods for visualizing a call over network 有权
公开(公告)号：US09749205B2
公开(公告)日：2017-08-29
申请号：US14500954
申请日：2014-09-29
申请人： Bin Zhao , Jonathan Li
发明人： Bin Zhao , Jonathan Li
IPC分类号： G06F15/16 , H04L12/26 , H04L29/06 , H04W4/16 , H04M3/432 , H04M3/56 , H04L12/18 , H04L12/24 , H04L12/721 , H04L12/925 , H04M3/22 , H04M7/00 , H04L12/58 , H04L12/841 , H04M1/253 , H04M1/725
CPC分类号： H04L43/0864 , H04L12/18 , H04L12/1827 , H04L12/1831 , H04L41/5038 , H04L43/045 , H04L43/062 , H04L43/0852 , H04L43/10 , H04L43/50 , H04L45/123 , H04L47/283 , H04L47/722 , H04L51/34 , H04L65/1066 , H04L65/4038 , H04M1/2535 , H04M1/72547 , H04M3/2236 , H04M3/432 , H04M3/563 , H04M3/565 , H04M7/0084 , H04M2250/62 , H04M2250/74 , H04W4/16
摘要： Systems and methods for visualization of a call over network (CON) are provided. In some embodiments, the visualization of a call over network may be effectuated by three functionalities: a readiness dialog box that enables the facilitation of the call, the inclusion of visualization and participant features within the call, and a visualized summary after the call. The readiness dialog box is presented to the callers prior to the onset of the call. It presents the other participant's and their status. It also enables the caller to send messages (both preconfigured and customized) to the other participants. Once sufficient participants have joined, the call may start. Once the call starts, it may be visualized by displaying on a single or multi channels, which caller is speaking, and any additional indications they may be providing. The caller may likewise be provided a set of participant features that allow the user to interact with the call. After the call concludes, a visualized summary of the call can then be generated. The summary includes any of the recording, transcriptions, scenario information, speaker information and the duration each speaker was talking, etc.

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