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    • 4. 发明授权
    • System for processing data with multiple virtual address and data word
lengths
    • 用于处理具有多个虚拟地址和数据字长度的数据的系统
    • US4868740A
    • 1989-09-19
    • US56885
    • 1987-06-03
    • Toyohiko KagimasaYoshiki MatsudaKikuo TakahashiSeiichi Yoshizumi
    • Toyohiko KagimasaYoshiki MatsudaKikuo TakahashiSeiichi Yoshizumi
    • G06F9/355
    • G06F9/342G06F9/30036
    • A data processor which specifies either of a predetermined maximum length of an adddress (a bits) and a length of an address less than the former length and at plural registers having a number of length of bits (r bits) of the maximum address length or greater. The data processor reads out lower-order d bits for data or r bits for an address of the one of the plural registers (7) specified by a first instruction to perform an arithmetic or logic operation, and writes the result into one of the plural registers. Moreover, the processor reads out bits having specified length of an address from the one of the plural registers specified in a second instruction to generate an a-bit address, and reads out d for data or r bits for an address from a main storage device (5) in response to the thus-generated address to write the d or r bits into one of the plural registers. Since the data length is consistently d bits irrespective of specified effective length of an address, direct data transfer is enabled between programs each having a different effective length of an address thereby facilitating extension of the length of a storage address and assuring compatibility with conventional data processors.
    • 数据处理器,其规定附加信息的预定最大长度(比特)和小于前一长度的地址的长度,以及指定具有最大地址长度的位长度(r比特)的数量的多个寄存器,或 更大 数据处理器为由第一指令指定的多个寄存器(7)之一的地址的数据或r位读出低位d位以执行算术或逻辑运算,并将结果写入多个 注册 此外,处理器从第二指令中指定的多个寄存器中的一个寄存器中读出具有指定地址长度的位,以产生一个位地址,并且从主存储装置读出数据或地址的r位 (5)响应于如此产生的地址将d或r位写入多个寄存器之一。 由于数据长度与地址的指定有效长度一致地为d位,因此在每个具有地址的不同有效长度的程序之间启用直接数据传输,从而有助于扩展存储地址的长度并确保与常规数据处理器的兼容性 。
    • 7. 发明授权
    • Data processing apparatus having a real memory region with a
corresponding fixed memory protection key value and method for
allocating memories therefor
    • 具有具有对应的固定存储器保护密钥值的实际存储区域和用于分配存储器的方法的数据处理装置
    • US5335334A
    • 1994-08-02
    • US751778
    • 1991-08-29
    • Kikuo TakahashiToyohiko KagimasaToshiaki Mori
    • Kikuo TakahashiToyohiko KagimasaToshiaki Mori
    • G06F12/14G06F12/06
    • G06F12/1466G06F12/1441
    • A region comprising a plurality of real pages in a part of a real storage unit is provided with a first key storage unit having a plurality of key storage entries each corresponding to one of the plurality of real pages, while a second region comprising a plurality of real pages in the second part of the real storage unit is provided with a second key storage unit having a single key storage entry. When a real address designated by an instruction to be executed belongs to the first region, an entry corresponding to this address is accessed by a storage protection control circuit. When this address belongs to the second region, the second key storage unit is accessed irrespective of the address. Further, a key within the accessed key information is compared with a key on a program status word (PSW) allocated to a program to determine whether the execution of the instruction is permitted.
    • 在真实存储单元的一部分中包括多个实际页面的区域设置有具有多个密钥存储条目的第一密钥存储单元,每个密钥存储条目对应于多个真实页面中的一个,而第二区域包括多个 真实存储单元的第二部分中的真实页面被提供有具有单个密钥存储条目的第二密钥存储单元。 当由要执行的指令指定的实际地址属于第一区域时,与该地址对应的条目由存储保护控制电路访问。 当该地址属于第二区域时,无论地址如何,访问第二密钥存储单元。 此外,将访问的密钥信息内的密钥与分配给程序的程序状态字(PSW)上的密钥进行比较,以确定是否允许指令的执行。
    • 8. 发明授权
    • Data processing apparatus with a virtual storage address boundary check
circuit
    • 具有虚拟存储地址边界检查电路的数据处理装置
    • US4851989A
    • 1989-07-25
    • US897403
    • 1986-08-18
    • Toyohiko KagimasaKikuo TakahashiYoshie OnoSeiichi Yoshizumi
    • Toyohiko KagimasaKikuo TakahashiYoshie OnoSeiichi Yoshizumi
    • G06F12/08G06F12/10G06F12/14
    • G06F12/10G06F12/145G06F2212/655
    • A data processing apparatus for an address boundary check circuit employed in combination with a virtual storage comprises a segment table register provided in association with an address translation table for storing an area discriminating signal indicating whether data to be checked in respect to the address boundary is assigned to unit areas resulting from division of the virtual storage and holding a limit address signal indicating the extent of the area assigned to data which requires an address boundary check of a virtual address accessing the data when the data is found in that area, a register holding a virtual base address for storing a register discriminating signal indicating whether or not the base address is for data to be checked in respect to the address boundary, and an address boundary check circuitry for deciding on the basis of the aforementioned first to third signals whether or not a virtual address calculated in response to an instruction erroneously goes beyond the address boundary.
    • 与虚拟存储器组合使用的用于地址边界检查电路的数据处理装置包括与地址转换表相关联地设置的段表寄存器,用于存储指示是否分配关于地址边界的数据被检查的区域鉴别信号 到由虚拟存储器分割而产生的单位区域,并且保存限制地址信号,该限制地址信号指示当在该区域中找到数据时,分配给需要对访问数据的虚拟地址进行地址边界检查的数据的区域的范围; 用于存储指示基地址是否用于关于地址边界要检查的数据的寄存器鉴别信号的虚拟基地址,以及用于基于上述第一至第三信号确定是否或者 不是响应于指令而计算的虚拟地址错误地超过t 他解决边界。
    • 10. 发明授权
    • Process of transferring file, process of gaining access to data and
process of writing data
    • 传输文件的过程,获取数据的过程和写入数据的过程
    • US5715452A
    • 1998-02-03
    • US357192
    • 1994-12-13
    • Toshiaki MoriToyohiko KagimasaKikuo TakahashiToshiyuki Ukai
    • Toshiaki MoriToyohiko KagimasaKikuo TakahashiToshiyuki Ukai
    • G06F12/00G06F3/06G06F13/00G11B20/10G06F17/30
    • G06F3/0613G06F3/0655G06F3/0674G11B20/10Y10S707/99931Y10S707/99952Y10S707/99953
    • To transfer a file comprising block data at high speed between sequential access type auxiliary memories, a file transmission program inquires of an operating system about the physical storage positions of the block data, determines a reading order to reduce the read access time on the basis of the results of inquiry, and issues read requests sequentially to the operating system according to the reading order. The file transmission program requests the operating system to transmit the read block data. The block data together with respective logical identification data, for example, logical block numbers, are transmitted to a receiving end which may be another computing system. The operating system at the receiving end is requested to secure the number of physical data blocks required to store the block data. The write order of the block data to the physical data blocks is then determined to reduce the access time and the block data are respectively stored in the secured physical data blocks according to the write order. Sequentially, a pair of the logical identifiers of each block data actually written to the data area and physical identification data of the data blocks are stored in the data area.
    • 为了在顺序访问型辅助存储器之间高速地传送包括块数据的文件,文件传输程序向操作系统询问块数据的物理存储位置,确定读取顺序以减少读取访问时间 查询结果,并根据阅读顺序将读取请求顺序发送到操作系统。 文件传输程序请求操作系统发送读块数据。 将块数据连同相应的逻辑识别数据(例如,逻辑块号)一起发送到可以是另一个计算系统的接收端。 请求接收端的操作系统确保存储块数据所需的物理数据块的数量。 然后确定块数据到物理数据块的写入顺序以减少访问时间,并且根据写入顺序将块数据分别存储在安全物理数据块中。 顺序地,实际写入数据区的每个块数据的一对逻辑标识符和数据块的物理标识数据被存储在数据区中。