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1. 发明授权

US4851989A Data processing apparatus with a virtual storage address boundary check circuit 失效
标题翻译：具有虚拟存储地址边界检查电路的数据处理装置
公开(公告)号：US4851989A
公开(公告)日：1989-07-25
申请号：US897403
申请日：1986-08-18
申请人： Toyohiko Kagimasa , Kikuo Takahashi , Yoshie Ono , Seiichi Yoshizumi
发明人： Toyohiko Kagimasa , Kikuo Takahashi , Yoshie Ono , Seiichi Yoshizumi
IPC分类号： G06F12/08 , G06F12/10 , G06F12/14
CPC分类号： G06F12/10 , G06F12/145 , G06F2212/655
摘要： A data processing apparatus for an address boundary check circuit employed in combination with a virtual storage comprises a segment table register provided in association with an address translation table for storing an area discriminating signal indicating whether data to be checked in respect to the address boundary is assigned to unit areas resulting from division of the virtual storage and holding a limit address signal indicating the extent of the area assigned to data which requires an address boundary check of a virtual address accessing the data when the data is found in that area, a register holding a virtual base address for storing a register discriminating signal indicating whether or not the base address is for data to be checked in respect to the address boundary, and an address boundary check circuitry for deciding on the basis of the aforementioned first to third signals whether or not a virtual address calculated in response to an instruction erroneously goes beyond the address boundary.
摘要翻译：与虚拟存储器组合使用的用于地址边界检查电路的数据处理装置包括与地址转换表相关联地设置的段表寄存器，用于存储指示是否分配关于地址边界的数据被检查的区域鉴别信号到由虚拟存储器分割而产生的单位区域，并且保存限制地址信号，该限制地址信号指示当在该区域中找到数据时，分配给需要对访问数据的虚拟地址进行地址边界检查的数据的区域的范围; 用于存储指示基地址是否用于关于地址边界要检查的数据的寄存器鉴别信号的虚拟基地址，以及用于基于上述第一至第三信号确定是否或者不是响应于指令而计算的虚拟地址错误地超过t 他解决边界。

2. 发明授权

US4868740A System for processing data with multiple virtual address and data word lengths 失效
标题翻译：用于处理具有多个虚拟地址和数据字长度的数据的系统
公开(公告)号：US4868740A
公开(公告)日：1989-09-19
申请号：US56885
申请日：1987-06-03
申请人： Toyohiko Kagimasa , Yoshiki Matsuda , Kikuo Takahashi , Seiichi Yoshizumi
发明人： Toyohiko Kagimasa , Yoshiki Matsuda , Kikuo Takahashi , Seiichi Yoshizumi
IPC分类号： G06F9/355
CPC分类号： G06F9/342 , G06F9/30036
摘要： A data processor which specifies either of a predetermined maximum length of an adddress (a bits) and a length of an address less than the former length and at plural registers having a number of length of bits (r bits) of the maximum address length or greater. The data processor reads out lower-order d bits for data or r bits for an address of the one of the plural registers (7) specified by a first instruction to perform an arithmetic or logic operation, and writes the result into one of the plural registers. Moreover, the processor reads out bits having specified length of an address from the one of the plural registers specified in a second instruction to generate an a-bit address, and reads out d for data or r bits for an address from a main storage device (5) in response to the thus-generated address to write the d or r bits into one of the plural registers. Since the data length is consistently d bits irrespective of specified effective length of an address, direct data transfer is enabled between programs each having a different effective length of an address thereby facilitating extension of the length of a storage address and assuring compatibility with conventional data processors.
摘要翻译：数据处理器，其规定附加信息的预定最大长度（比特）和小于前一长度的地址的长度，以及指定具有最大地址长度的位长度（r比特）的数量的多个寄存器，或更大数据处理器为由第一指令指定的多个寄存器（7）之一的地址的数据或r位读出低位d位以执行算术或逻辑运算，并将结果写入多个注册此外，处理器从第二指令中指定的多个寄存器中的一个寄存器中读出具有指定地址长度的位，以产生一个位地址，并且从主存储装置读出数据或地址的r位（5）响应于如此产生的地址将d或r位写入多个寄存器之一。由于数据长度与地址的指定有效长度一致地为d位，因此在每个具有地址的不同有效长度的程序之间启用直接数据传输，从而有助于扩展存储地址的长度并确保与常规数据处理器的兼容性。

3. 发明授权

US4679140A Data processor with control of the significant bit lengths of general purpose registers 失效
标题翻译：数据处理器可控制通用寄存器的有效位长度
公开(公告)号：US4679140A
公开(公告)日：1987-07-07
申请号：US684785
申请日：1984-12-21
申请人： Shizuo Gotou , Toyohiko Kagimasa , Seiichi Yoshizumi , Yooichi Shintani
发明人： Shizuo Gotou , Toyohiko Kagimasa , Seiichi Yoshizumi , Yooichi Shintani
IPC分类号： G06F9/318 , G06F9/355 , G06F12/04
CPC分类号： G06F9/342 , G06F9/30036 , G06F9/30181
摘要： A mode register stores a mode bit for each of the general registers, an access circuit accesses the general registers and the mode register so that a general register designated by an instruction and a corresponding mode bit are read out together. A data use circuit or a data supply circuit connected to the general registers includes a circuit portion which effectively changes the significant bit length of the data read out of the designated general register or of the data to be written into the designated general register.
摘要翻译：模式寄存器存储每个通用寄存器的模式位，访问电路访问通用寄存器和模式寄存器，使得由指令指定的通用寄存器和相应的模式位一起读出。连接到通用寄存器的数据使用电路或数据提供电路包括有效地改变从指定通用寄存器读出的数据或要写入指定通用寄存器的数据的有效位长度的电路部分。

4. 发明授权

US4876646A Data processor having multilevel address translation tables 失效
标题翻译：具有多级地址转换表的数据处理器
公开(公告)号：US4876646A
公开(公告)日：1989-10-24
申请号：US810189
申请日：1985-12-18
申请人： Shizuo Gotou , Toyohiko Kagimasa , Seiichi Yoshizumi
发明人： Shizuo Gotou , Toyohiko Kagimasa , Seiichi Yoshizumi
IPC分类号： G06F12/02 , G06F12/10
CPC分类号： G06F12/1009 , G06F12/0292
摘要： An information processing system including a group of translation tables in a multilevel structure for achieving address translation from a virtual address into a real address, a control register for keeping a starting point address data of a translation table located at a highest level among the address translation tables and a level data indicating a level (n) of the translation table at the highest level among the group of translation tables, and a unit for sequentially accessing the address translation tables at levels lower than the level (n) indicated by the level data in the control register based on the starting point address data and a virtual address to be translated, thereby translating the virtual address into a real address.
摘要翻译：一种信息处理系统，包括用于实现从虚拟地址到实际地址的地址转换的多级结构中的一组转换表，用于保持地址转换中位于最高级别的翻译表的起点地址数据的控制寄存器表和表示该组转换表中的最高级别的翻译表的级别（n）的级别数据，以及用于以低于由级别数据指示的级别（n）顺序访问地址转换表的单元在控制寄存器中基于起始点地址数据和要转换的虚拟地址，从而将虚拟地址转换为实际地址。

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