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1. 发明授权

US08525246B2 Semiconductor storage device and method of manufacturing the same 有权
标题翻译：半导体存储装置及其制造方法
公开(公告)号：US08525246B2
公开(公告)日：2013-09-03
申请号：US12724802
申请日：2010-03-16
申请人： Yoshiko Kato , Hiroyuki Kutsukake , Kikuko Sugimae , Yasuhiko Matsunaga
发明人： Yoshiko Kato , Hiroyuki Kutsukake , Kikuko Sugimae , Yasuhiko Matsunaga
IPC分类号： H01L29/76
CPC分类号： H01L27/11521
摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a first device isolation/insulation film formed in a trench, the trench formed in the semiconductor layer, with a first direction taken as a longitudinal direction; a device formation region formed by separating the semiconductor layer by the first device isolation/insulation film with the first direction taken as a longitudinal direction; and a memory transistor disposed on the device formation region. The first device isolation/insulation film and the device formation region have an impurity of a first conductivity type. An impurity concentration of the impurity of the first conductivity type in the first device isolation/insulation film is higher than that in the device formation region.
摘要翻译：非易失性半导体存储器件包括：半导体衬底; 形成在半导体衬底上的半导体层; 形成在沟槽中的第一器件隔离/绝缘膜，形成在半导体层中的沟槽，第一方向作为纵向方向; 通过第一装置隔离/绝缘膜将第一方向作为纵向方向分离半导体层而形成的器件形成区域; 以及设置在器件形成区域上的存储晶体管。第一器件隔离/绝缘膜和器件形成区具有第一导电类型的杂质。第一器件隔离/绝缘膜中的第一导电类型的杂质的杂质浓度高于器件形成区域中的杂质浓度。

2. 发明申请

US20100314677A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100314677A1
公开(公告)日：2010-12-16
申请号：US12724802
申请日：2010-03-16
申请人： Yoshiko KATO , Hiroyuki Kutsukake , Kikuko Sugimae , Yasuhiko Matsunaga
发明人： Yoshiko KATO , Hiroyuki Kutsukake , Kikuko Sugimae , Yasuhiko Matsunaga
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11521
摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a first device isolation/insulation film formed in a trench, the trench formed in the semiconductor layer, with a first direction taken as a longitudinal direction; a device formation region formed by separating the semiconductor layer by the first device isolation/insulation film with the first direction taken as a longitudinal direction; and a memory transistor disposed on the device formation region. The first device isolation/insulation film and the device formation region have an impurity of a first conductivity type. An impurity concentration of the impurity of the first conductivity type in the first device isolation/insulation film is higher than that in the device formation region.
摘要翻译：非易失性半导体存储器件包括：半导体衬底; 形成在半导体衬底上的半导体层; 形成在沟槽中的第一器件隔离/绝缘膜，形成在半导体层中的沟槽，第一方向作为纵向方向; 通过第一装置隔离/绝缘膜将第一方向作为纵向方向分离半导体层而形成的器件形成区域; 以及设置在器件形成区域上的存储晶体管。第一器件隔离/绝缘膜和器件形成区具有第一导电类型的杂质。第一器件隔离/绝缘膜中的第一导电类型的杂质的杂质浓度高于器件形成区域中的杂质浓度。

3. 发明授权

US08400812B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08400812B2
公开(公告)日：2013-03-19
申请号：US13231510
申请日：2011-09-13
申请人： Hiroyuki Kutsukake , Kikuko Sugimae , Mitsuhiro Noguchi
发明人： Hiroyuki Kutsukake , Kikuko Sugimae , Mitsuhiro Noguchi
IPC分类号： G11C5/06 , G11C5/02 , G11C16/04
CPC分类号： G11C16/0483 , G11C5/063 , G11C8/14 , H01L27/0207 , H01L27/088 , H01L27/11519 , H01L27/11529
摘要： According to one embodiment, a semiconductor memory device includes a memory array and a peripheral circuit. The memory array has a plurality of memory cells, word lines, and bit lines, in which a first, second, and third blocks are set in the order along the bit line. The peripheral circuit has a transistor group. The transistor group includes a first transfer transistor belonging to the first block, a second transfer transistor belonging to the second block, and a third transfer transistor belonging to the third block. The first, second, and third transfer transistors share the other of a source and a drain of each. With regard to a direction in which either of the source and the drain is connected to the other in each of the first, second, and third transfer transistors, the directions of the adjacent transfer transistors are different from each other by 90° or 180°.
摘要翻译：根据一个实施例，半导体存储器件包括存储器阵列和外围电路。存储器阵列具有多个存储单元，字线和位线，其中按照位线的顺序设置第一，第二和第三块。外围电路具有晶体管组。晶体管组包括属于第一块的第一转移晶体管，属于第二块的第二转移晶体管和属于第三块的第三转移晶体管。第一，第二和第三转移晶体管共享每个的源极和漏极中的另一个。关于源极和漏极中的任一个与第一，第二和第三转移晶体管中的每一个连接到另一个的方向，相邻的转移晶体管的方向彼此相差90°或180° 。

4. 发明授权

US07939908B2 High-voltage transistor having shielding gate 有权
标题翻译：具有屏蔽门的高电压晶体管
公开(公告)号：US07939908B2
公开(公告)日：2011-05-10
申请号：US11510584
申请日：2006-08-28
申请人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
发明人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
IPC分类号： H01L21/76
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
摘要翻译：半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。

5. 发明授权

US07504294B2 Method of manufacturing an electrically erasable programmable read-only memory (EEPROM) 有权
标题翻译：制造电可擦除可编程只读存储器（EEPROM）的方法
公开(公告)号：US07504294B2
公开(公告)日：2009-03-17
申请号：US10881180
申请日：2004-07-01
申请人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
发明人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
IPC分类号： H01L21/8238
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.
摘要翻译：半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

6. 发明授权

US07417281B2 Semiconductor device with a selection gate and a peripheral gate 有权
标题翻译：具有选择栅极和外围栅极的半导体器件
公开(公告)号：US07417281B2
公开(公告)日：2008-08-26
申请号：US11733488
申请日：2007-04-10
申请人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
发明人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
IPC分类号： H01L29/94
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.
摘要翻译：半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

7. 发明申请

US20060202257A1 Nonvolatile semiconductor memory device 失效
公开(公告)号：US20060202257A1
公开(公告)日：2006-09-14
申请号：US11430170
申请日：2006-05-09
申请人： Hiroyuki Kutsukake , Kikuko Sugimae
发明人： Hiroyuki Kutsukake , Kikuko Sugimae
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/764 , H01L27/115 , H01L27/11519 , H01L27/11524
摘要： A nonvolatile semiconductor memory device including a memory cell and a selection transistor, and the memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate formed on the substrate via a second gate insulation film, and a pair of second diffusion layers formed in the substrate positioned on the opposite sides of the selection gate and one of which is electrically connected to one of the pair of first diffusion layers.

8. 发明申请

US20060197160A1 Nonvolatile semiconductor memory device 审中-公开
公开(公告)号：US20060197160A1
公开(公告)日：2006-09-07
申请号：US11429311
申请日：2006-05-08
申请人： Kikuko Sugimae , Hiroyuki Kutsukake
发明人： Kikuko Sugimae , Hiroyuki Kutsukake
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate•wiring including a first portion constituted of the same conductive layer as the first conductive layer, and a second portion constituted of the same conductive layer as the second conductive layer, and a second diffusion layer formed in the substrate, facing the second portion of the selection gate•wiring.

9. 发明授权

US07064394B2 Nonvolatile semiconductor memory device 失效
公开(公告)号：US07064394B2
公开(公告)日：2006-06-20
申请号：US11304580
申请日：2005-12-16
申请人： Kikuko Sugimae , Hiroyuki Kutsukake
发明人： Kikuko Sugimae , Hiroyuki Kutsukake
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate•wiring including a first portion constituted of the same conductive layer as the first conductive layer, and a second portion constituted of the same conductive layer as the second conductive layer, and a second diffusion layer formed in the substrate, facing the second portion of the selection gate•wiring.

10. 发明申请

US20050036353A1 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050036353A1
公开(公告)日：2005-02-17
申请号：US10885613
申请日：2004-07-08
申请人： Kikuko Sugimae , Hiroyuki Kutsukake
发明人： Kikuko Sugimae , Hiroyuki Kutsukake
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/21
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate•wiring including a first portion constituted of the same conductive layer as the first conductive layer, and a second portion constituted of the same conductive layer as the second conductive layer, and a second diffusion layer formed in the substrate, facing the second portion of the selection gate•wiring.
摘要翻译：提供了用于选择存储单元的存储单元和选择晶体管。存储单元包括通过第一栅极绝缘膜在半导体衬底上形成的浮置栅极，位于浮置栅极的相对侧并形成在衬底中的一对第一扩散层，形成在相对侧上的第一和第二控制栅极的栅极驱动浮栅，以及形成在第一和第二控制栅极与浮置栅极之间的栅极间绝缘膜。选择晶体管包括选择栅极布线，其包括由与第一导电层相同的导电层构成的第一部分和由与第二导电层相同的导电层构成的第二部分，以及形成在基板中的第二扩散层，面向选择门的第二部分。

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