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1. 发明授权

US06492203B1 Semiconductor device and method of fabrication thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06492203B1
公开(公告)日：2002-12-10
申请号：US09680369
申请日：2000-10-05
申请人： Yoshiaki Wakashima , Naoki Fukutomi , Kazuhisa Suzuki , Toshio Yamazaki , Tsutomu Kitakatsu , Susumu Naoyuki , Akinari Kida
发明人： Yoshiaki Wakashima , Naoki Fukutomi , Kazuhisa Suzuki , Toshio Yamazaki , Tsutomu Kitakatsu , Susumu Naoyuki , Akinari Kida
IPC分类号： H01L2144
CPC分类号： H01L24/85 , H01L21/4803 , H01L23/13 , H01L23/24 , H01L23/3114 , H01L23/3128 , H01L23/36 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L29/0657 , H01L2224/05624 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48624 , H01L2224/85 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15153 , H01L2924/15157 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/157 , H01L2924/181 , H01L2224/78 , H01L2924/00
摘要： A semiconductor device fabrication process comprising an encapsulation step of carrying out encapsulation by vacuum pressure differential printing by the use of a liquid resin encapsulant containing a solvent in an amount of from 5% by weight to 50% by weight, and preferably from 25% by weight to 50% by weight. The encapsulation step comprises: printing the liquid resin encapsulant by vacuum pressure differential printing in such a way that; the encapsulant covers at least an internal connecting terminal provided on a substrate, a semiconductor chip, and a wire interconnecting the internal connecting terminal and the semiconductor chip; and that the thickness of the encapsulant lying above the wire at the highest position of the wire comes to be at least 0.8 times the thickness of the encapsulant lying beneath the wire at the same position; and curing or drying the encapsulant.
摘要翻译：一种半导体器件制造方法，包括通过真空压差印刷进行封装的封装步骤，所述封装步骤通过使用含有溶剂的液体树脂密封剂，其量为5重量％至50重量％，优选25重量％重量至50％重量。封装步骤包括：通过真空压差印刷印刷液态树脂密封剂，密封剂至少覆盖设置在基板上的内部连接端子，半导体芯片和互连内部连接端子和半导体芯片的布线; 并且位于电线最高位置处的线上方的密封剂的厚度至少为位于相同位置下方的密封剂厚度的至少0.8倍; 并固化或干燥密封剂。

2. 发明授权

US06268648B1 Board for mounting semiconductor element, method for manufacturing the same, and semiconductor device 失效
标题翻译：用于安装半导体元件的板，其制造方法和半导体器件
公开(公告)号：US06268648B1
公开(公告)日：2001-07-31
申请号：US09423062
申请日：1999-10-29
申请人： Naoki Fukutomi , Yoshiaki Wakashima , Susumu Naoyuki , Akinari Kida
发明人： Naoki Fukutomi , Yoshiaki Wakashima , Susumu Naoyuki , Akinari Kida
IPC分类号： H01L2972
CPC分类号： H01L24/85 , H01L21/4803 , H01L23/13 , H01L23/24 , H01L23/3121 , H01L23/3128 , H01L23/36 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L24/73 , H01L29/0657 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/131 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48799 , H01L2224/48824 , H01L2224/48847 , H01L2224/73265 , H01L2224/85 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15153 , H01L2924/15157 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/18165 , H01L2924/3025 , H05K3/0014 , H01L2224/78 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2924/01004
摘要： A semiconductor device comprising a substrate with a cavity portion for mounting a semiconductor chip is provided to achieve a high reliability and to decrease a size and a fabricating cost. The cavity portion capable of mounting the semiconductor chip (1) at the center portion of the substrate is formed by press forming with a projected portion (13a) of a die (13) while adhering a press shapeable wiring body comprising a copper wiring (12) which becomes wiring material, a barrier layer (11) such as nickel alloy or the like, and a copper foil (10) which is a carrier layer, to a plastic substrate (14,15), so as to have wiring (2) buried into a surface of the substrate and to form a ramp between an inner connection terminal portion connecting to the semiconductor chip (1) and an external connection terminal portion connecting to an external connection terminals (5), the internal and external connection terminal portions being two edge portions of the wiring (2).
摘要翻译：提供包括具有用于安装半导体芯片的空腔部分的基板的半导体器件以实现高可靠性并且减小尺寸和制造成本。能够将半导体芯片（1）安装在基板的中心部分的空腔部分通过压模成型而与模具（13）的突出部分（13a）粘合，同时将包括铜布线（12）），诸如镍合金等的阻挡层（11）和作为载体层的铜箔（10）连接到塑料基板（14,15），从而具有布线（2）），并且在连接到半导体芯片（1）的内部连接端子部分和连接到外部连接端子（5）的外部连接端子部分之间形成斜坡，内部和外部连接端子部分是布线（2）的两个边缘部分。

3. 发明授权

US06708398B2 Substrate for use in package of semiconductor device, semiconductor package using the substrate, and methods for manufacturing the substrate and the semiconductor package 失效
标题翻译：用于半导体器件封装的衬底，使用衬底的半导体封装，以及用于制造衬底和半导体封装的方法
公开(公告)号：US06708398B2
公开(公告)日：2004-03-23
申请号：US09907639
申请日：2001-07-19
申请人： Yoshiaki Wakashima , Naoki Fukutomi , Kazuhisa Suzuki , Takeshi Funaki
发明人： Yoshiaki Wakashima , Naoki Fukutomi , Kazuhisa Suzuki , Takeshi Funaki
IPC分类号： H05K300
CPC分类号： H01L21/486 , H01L23/49816 , H01L23/49866 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/07802 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , Y10T29/49124 , Y10T29/49147 , Y10T29/49155 , Y10T29/49204 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A substrate for use in a semiconductor package is fabricated by preparing a composite metal laminate consisting of a first metal layer, a second metal layer, and a carrier layer positioned in this order. The first metal layer has etching characteristics different to those of the second metal layer with respect to the same etchant. The first metal layer is selectively etched until the second metal layer is exposed, thereby forming pillar-like interconnections. The gap between the interconnections is then filled with a resin so as to form a resin base with interconnections. The carrier layer is removed from the second metal layer, and the second metal layer is selectively etched until the first metal layer or the resin base is exposed, thereby forming a conductive pattern on the resin base.
摘要翻译：通过制备由第一金属层，第二金属层和依次定位的载体层组成的复合金属层叠体，制造用于半导体封装的基板。第一金属层相对于相同的蚀刻剂具有与第二金属层不同的蚀刻特性。选择性地蚀刻第一金属层直到第二金属层被暴露，从而形成柱状互连。然后用树脂填充互连之间的间隙，以形成具有互连的树脂基底。从第二金属层去除载体层，并且选择性地蚀刻第二金属层直到暴露第一金属层或树脂基底，从而在树脂基底上形成导电图案。

4. 发明授权

US4982265A Semiconductor integrated circuit device and method of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US4982265A
公开(公告)日：1991-01-01
申请号：US209739
申请日：1988-06-22
申请人： Masayuki Watanabe , Toshio Sugano , Seiichiro Tsukui , Takashi Ono , Yoshiaki Wakashima
发明人： Masayuki Watanabe , Toshio Sugano , Seiichiro Tsukui , Takashi Ono , Yoshiaki Wakashima
IPC分类号： G11C5/00 , H01L23/495 , H01L25/065 , H01L25/10 , H05K1/14 , H05K3/34 , H05K3/36
CPC分类号： H05K1/141 , G11C5/00 , H01L23/49572 , H01L25/0657 , H01L25/105 , H01L2224/1147 , H01L2225/06517 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06579 , H01L2225/06582 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2924/01055 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H05K2201/10515 , H05K2201/10681 , H05K2203/1572 , H05K3/3447 , H05K3/368
摘要： In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
摘要翻译：在本发明中，存储芯片通过TAB（磁带自动键合）以堆叠的方式粘合在一起，并且由芯片和引线形成像SOP（小外线封装）的多存储器芯片和引线复合体，由此存储器高封装密度的模块可以通过扁平封装技术实现。

5. 发明授权

US4977441A Semiconductor device and tape carrier 失效
标题翻译：半导体器件和带载体
公开(公告)号：US4977441A
公开(公告)日：1990-12-11
申请号：US515344
申请日：1990-04-30
申请人： Hideya Ohtani , Toshimitsu Momoi , Eiji Ooi , Shuhei Sakuraba , Masayuki Morita , Yoshiaki Wakashima
发明人： Hideya Ohtani , Toshimitsu Momoi , Eiji Ooi , Shuhei Sakuraba , Masayuki Morita , Yoshiaki Wakashima
IPC分类号： H01L21/60 , H01L23/495 , H01L23/498 , H01L23/58
CPC分类号： H01L22/32 , H01L23/49572 , H01L23/4985 , H01L24/24 , H01L24/82 , H01L24/86 , H01L2224/24137 , H01L2224/24226 , H01L2224/7665 , H01L2224/7965 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14
摘要： According to the present invention, a tape carrier is prepared which comprises a power trunk line including an electric connection as a branch of a power lead for each tape carrier unit and a ground trunk line having an electric connection as a branch of a ground lead for each tape carrier unit, the power and trunk lines being continuously formed along the longitudinal direction of the tape carrier, and a lead for a control signal for establishing an electric conduction along the longitudinal direction of the tape carrier via an aging wiring for semiconductor pellets to conduct a simultaneous multipoint (gang) bonding on the tape carrier, the control signal lead being formed on the tape carrier. By mounting the semiconductor pellets having the aging wiring on the tape carrier, it is enabled to apply the power voltage and to supply the control signal to each of the plurality of the semiconductor pellets, and hence the operation test can be simultaneously conducted for the semiconductor pellets mounted on the tape carrier having an arbitrary length. This provision enables a plurality of semiconductor devices mounted on the tape carrier to be subjected to an aging, namely, a reliability test under a thermal environment and in the operating state, and hence an efficient reliability test can be achieved with an effect of the mass production. Consequently, a highly reliable semiconductor device can be provided.
摘要翻译：根据本发明，制备了一种载带，其包括一个电源主干线，该电源主干线包括作为用于每个载带单元的电源引线的分支的电连接，以及具有电连接作为接地引线的分支的地线，每个载带单元，沿着带载体的纵向方向连续形成的电源线和主干线，以及用于控制信号的引线，用于经由用于半导体芯片的老化布线沿着带状物的纵向方向建立导电，在带载体上进行同时多点（组合）接合，控制信号引线形成在载带上。通过将具有老化布线的半导体芯片安装在带载体上，能够施加电源电压并将控制信号提供给多个半导体颗粒中的每一个，因此可以同时进行半导体的操作测试安装在具有任意长度的带状载体上的颗粒。通过这样的配置，能够使安装在带载体上的多个半导体装置经受老化，即在热环境下和运行状态下的可靠性试验，因此可以实现质量的有效的可靠性试验生产。因此，可以提供高度可靠的半导体器件。

6. 发明授权

US5028986A Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices 失效
标题翻译：具有多个堆叠半导体器件的半导体器件和半导体模块
公开(公告)号：US5028986A
公开(公告)日：1991-07-02
申请号：US288955
申请日：1988-12-23
申请人： Toshio Sugano , Kohji Nagaoka , Seiichiro Tsukui , Yoshiaki Wakashima , Michio Tanimoto , Masayuki Watanabe , Suguru Sakaguchi , Kunihiko Nishi , Aizo Kaneda , Kohji Serizawa , Michiharu Honda , Tohru Yoshida , Takeshi Komaru , Atsushi Nakamura
发明人： Toshio Sugano , Kohji Nagaoka , Seiichiro Tsukui , Yoshiaki Wakashima , Michio Tanimoto , Masayuki Watanabe , Suguru Sakaguchi , Kunihiko Nishi , Aizo Kaneda , Kohji Serizawa , Michiharu Honda , Tohru Yoshida , Takeshi Komaru , Atsushi Nakamura
IPC分类号： G11C5/00 , H01L23/498 , H01L25/065 , H05K1/14 , H05K1/18 , H05K3/34 , H05K3/36
CPC分类号： G11C5/02 , G11C5/00 , G11C5/06 , H01L23/49805 , H01L25/0657 , H01L2224/16 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06572 , H01L2225/06579 , H01L2225/06596 , H01L2924/07811 , H01L2924/09701 , H05K1/144 , H05K1/182 , H05K3/3421 , H05K3/363
摘要： There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.
摘要翻译：存在增加需要大容量存储器的器件的面积的趋势，其由半导体存储器占据。这种趋势阻碍了设备尺寸的减小。本发明旨在提供一种能够在最小化安装面积的同时具有高集成度，高密度和大容量的存储器。为了实现这种记忆，现有技术的TAB（磁带自动接合）被安装在导电连接器上，并且由TAB和连接器组成的多个结构被堆叠。此外，将TAB安装在其上的连接器构造成使得堆叠的TAB的独立端子可能不会短路。

7. 发明授权

US4322593A Apparatus for pre-heating resin tablet 失效
标题翻译：树脂片预热装置
公开(公告)号：US4322593A
公开(公告)日：1982-03-30
申请号：US097126
申请日：1979-11-26
申请人： Kunihiko Nishi , Yoshiaki Wakashima , Akira Suzuki , Aizo Kaneda , Sumumu Tuzuku
发明人： Kunihiko Nishi , Yoshiaki Wakashima , Akira Suzuki , Aizo Kaneda , Sumumu Tuzuku
IPC分类号： B29C35/02 , B29B13/02 , B29C45/02 , B29C45/17 , B29K101/10 , G05D24/02 , H05B6/56 , H05B6/50
CPC分类号： B29B13/02 , G05D24/02 , Y10S264/46
摘要： An apparatus for pre-heating resin tablets comprising a resin tablet heater, a switch for setting a reference softening degree and a softening degree detector for the resin tablet. The detector includes a pressure source and a pressure transmitting member coupled to the pressure source and adapted for contact with the resin tablet. The pressure transmitting member is movable a distance representative of the softening degree of the resin tablet being heated due to deformation of the resin tablet.
摘要翻译：一种用于预热树脂片的设备，包括树脂片加热器，用于设定参考软化度的开关和用于树脂片的软化度检测器。检测器包括压力源和连接到压力源并适于与树脂片接触的压力传递构件。压力传递构件可移动一定距离，代表由于树脂片的变形而被加热的树脂片的软化度。

8. 发明授权

US4064289A Method of making a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4064289A
公开(公告)日：1977-12-20
申请号：US606354
申请日：1975-08-21
申请人： Takashi Yokoyama , Yasuo Miyadera , Nobuhiko Shito , Hiroshi Suzuki , Yoshiaki Wakashima
发明人： Takashi Yokoyama , Yasuo Miyadera , Nobuhiko Shito , Hiroshi Suzuki , Yoshiaki Wakashima
IPC分类号： C08L79/04 , H01B3/30 , H01L21/312 , H01L23/29 , H01L23/31 , H01L23/30
CPC分类号： H01B3/306 , C08L79/04 , H01L21/312 , H01L23/293 , H01L23/3171 , H01L2924/0002 , Y10T428/31721
摘要： Method of making a semiconductor device which includes applying a solution of a heterocyclic ring-containing polymer in an organic solvent to a desired surface of a semiconductor body and removing the organic solvent from the solution by heat thereby to form a coating of a polymer on the surface, wherein the polymer is a reaction product of a diamine represented by the formula: ##STR1## with a tetracarboxylic acid or anhydride of it. Since the coating exhibits good thermal stability and good electrical properties when applied to the surface of the semiconductor, it is useful as a passivating film.
摘要翻译：制造半导体器件的方法包括将含有杂环的聚合物在有机溶剂中的溶液施加到半导体本体的所需表面，并通过热从溶液中除去有机溶剂，从而形成聚合物的涂层表面，其中聚合物是由下式表示的二胺与四羧酸或其酸酐的反应产物。由于当涂覆在半导体的表面上时，涂层具有良好的热稳定性和良好的电学性能，因此可用作钝化膜。

9. 发明授权

US3946427A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US3946427A
公开(公告)日：1976-03-23
申请号：US514956
申请日：1974-10-15
申请人： Hideo Iwasawa , Yoshiaki Wakashima , Hideo Inayoshi
发明人： Hideo Iwasawa , Yoshiaki Wakashima , Hideo Inayoshi
IPC分类号： H01L21/312 , H01L23/30
CPC分类号： H01L21/3121
摘要： In a semiconductor device, the surface of a semiconductor element is covered with a silicone varnish in which the side chain radical ratio between methyl radicals and phenyl radicals is 20:1 or greater, whereby the element is effectively shielded from the external moisture.
摘要翻译：在半导体器件中，半导体元件的表面被甲基自由基和苯基之间的侧链自由基比为20:1或更大的硅氧烷清漆覆盖，由此元件被有效地屏蔽外部水分。

10. 发明授权

US5910685A Semiconductor memory module having double-sided stacked memory chip layout 失效
公开(公告)号：US5910685A
公开(公告)日：1999-06-08
申请号：US984330
申请日：1997-12-03
申请人： Masayuki Watanabe , Toshio Sugano , Seiichiro Tsukui , Takashi Ono , Yoshiaki Wakashima
发明人： Masayuki Watanabe , Toshio Sugano , Seiichiro Tsukui , Takashi Ono , Yoshiaki Wakashima
IPC分类号： G11C5/00 , H01L23/495 , H01L25/065 , H01L25/10 , H05K1/14 , H05K3/34 , H05K3/36 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： G11C5/02 , G11C5/00 , G11C5/04 , G11C5/06 , G11C8/12 , H01L23/49572 , H01L24/16 , H01L24/50 , H01L25/0657 , H01L25/105 , H05K1/141 , H01L2224/0401 , H01L2224/05558 , H01L2224/1147 , H01L2224/13099 , H01L2224/16 , H01L2224/16245 , H01L2225/06513 , H01L2225/06517 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06579 , H01L2225/06582 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01051 , H01L2924/01055 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H05K2201/10515 , H05K2201/10681 , H05K2203/1572 , H05K3/3447 , H05K3/368
摘要： In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.

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