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1. 发明授权

US08487352B2 Metal oxide semiconductor (MOS) transistors having a recessed gate electrode 有权
标题翻译：具有凹陷栅电极的金属氧化物半导体（MOS）晶体管
公开(公告)号：US08487352B2
公开(公告)日：2013-07-16
申请号：US13236389
申请日：2011-09-19
申请人： Yong-Sung Kim , Tae-Young Chung
发明人： Yong-Sung Kim , Tae-Young Chung
IPC分类号： H01L27/148
CPC分类号： H01L29/7834 , H01L29/51 , H01L29/66621
摘要： A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region.
摘要翻译：金属氧化物半导体（MOS）包括设置在半导体衬底中以限定有源区的隔离层。源极区域和漏极区域设置在有源区域的两侧，使得从源极区域到漏极区域限定第一方向。通道凹槽设置在源区和漏区之间的有源区中。当从沿着与第一方向正交的第二方向截取的横截面视图观察时，通道凹部具有凸形表面。栅电极填充通道凹槽并沿第二方向跨过有源区。栅极绝缘层插入在栅电极和有源区之间。

2. 发明授权

US07488654B2 Fabrication of local damascene finFETs using contact type nitride damascene mask 失效
公开(公告)号：US07488654B2
公开(公告)日：2009-02-10
申请号：US11508992
申请日：2006-08-24
申请人： Yong-Sung Kim , Tae-Young Chung
发明人： Yong-Sung Kim , Tae-Young Chung
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L27/1211 , H01L29/66795
摘要： Disclosed are methods for forming FinFETs using a first hard mask pattern to define active regions and a second hard mask to protect portions of the insulating regions between active regions. The resulting field insulating structure has three distinct regions distinguished by the vertical offset from a reference plane defined by the surface of the active regions. These three regions will include a lower surface found in the recessed openings resulting from the damascene etch, an intermediate surface and an upper surface on the remaining portions of the lateral field insulating regions. The general correspondence between the reference plane and the intermediate surface will tend to suppress or eliminate residual gate electrode materials from this region during formation of the gate electrodes, thereby improving the electrical isolation between adjacent active regions and improving the performance of the resulting semiconductor devices.

3. 发明授权

US07413943B2 Method of fabricating gate of fin type transistor 有权
标题翻译：鳍型晶体管栅极的制造方法
公开(公告)号：US07413943B2
公开(公告)日：2008-08-19
申请号：US11460905
申请日：2006-07-28
申请人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
发明人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
IPC分类号： H01L21/336 , H01L31/062
CPC分类号： H01L21/823437 , H01L21/823412 , H01L29/66795 , H01L29/7851
摘要： A method of fabricating a gate of a fin type transistor includes forming hard masks to define active regions of a substrate. A shallow trench isolation method is performed to form a first device separation layer, and then an etch-back process is performed such that the active regions protrude. Sidewall protection layers are formed on sidewalls of the active region, and a second device separation layer is formed thereon, thereby obtaining a device isolation region. The sidewall protection layers include an insulation material with an etch selectivity with respect to an insulation material composing the device isolation region. The device isolation region is selectively etched to form recesses for a fin type active region. Dry etching and wet etching are performed on the silicon nitride to remove the hard masks and the sidewall protection layers, respectively. Gates are formed to fill the recesses.
摘要翻译：制造鳍式晶体管的栅极的方法包括形成硬掩模以限定衬底的有源区。执行浅沟槽隔离方法以形成第一器件分离层，然后执行回蚀处理，使得有源区域突出。侧壁保护层形成在有源区的侧壁上，并且在其上形成第二器件分离层，从而获得器件隔离区。侧壁保护层包括相对于构成器件隔离区域的绝缘材料具有蚀刻选择性的绝缘材料。选择性地蚀刻器件隔离区以形成翅片型有源区的凹槽。对氮化硅进行干蚀刻和湿蚀刻以分别去除硬掩模和侧壁保护层。形成门以填充凹部。

4. 发明授权

US07368778B2 DRAM having at least three layered impurity regions between channel holes and method of fabricating same 失效
标题翻译：在通道孔之间具有至少三层杂质区的DRAM及其制造方法
公开(公告)号：US07368778B2
公开(公告)日：2008-05-06
申请号：US11210705
申请日：2005-08-25
申请人： Jin-Woo Lee , Yong-Sung Kim , Tae-Young Chung
发明人： Jin-Woo Lee , Yong-Sung Kim , Tae-Young Chung
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/0847 , H01L21/76895 , H01L27/10852 , H01L27/10876 , H01L27/10888 , H01L29/66621 , H01L29/66659
摘要： Disclosed is a dynamic random access memory (DRAM) comprising a transistor having channel holes formed in the channel region thereof and cell gate structures formed in the channel holes. At least three layered impurity regions are formed in a semiconductor substrate between the channel holes and the at least three layered impurity regions form a source region for the transistor.
摘要翻译：公开了一种动态随机存取存储器（DRAM），其包括晶体管，该晶体管具有在其沟道区中形成的沟道孔，并且形成在沟道孔中的单元栅极结构。在通道孔和至少三层杂质区之间的半导体衬底中形成至少三层杂质区，形成晶体管的源极区。

5. 发明申请

US20140103482A1 SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNELS AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：具有垂直通道的半导体器件及其制造方法
公开(公告)号：US20140103482A1
公开(公告)日：2014-04-17
申请号：US14109517
申请日：2013-12-17
申请人： Yong-Sung Kim , Tae-Young CHUNG , Soo-Ho SHIN
发明人： Yong-Sung Kim , Tae-Young CHUNG , Soo-Ho SHIN
IPC分类号： H01L29/06 , H01L27/088
CPC分类号： H01L21/28123 , H01L21/76224 , H01L27/088 , H01L27/0886 , H01L27/10826 , H01L27/10879 , H01L29/0649 , H01L29/0653 , H01L29/4238 , H01L29/66795 , H01L29/7802 , H01L29/7827 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
摘要翻译：一种制造半导体器件的方法，该半导体器件能够防止由有源区的长轴与元件隔离层相交的栅电极引起的泄漏电流，并且还具有垂直沟道以提供足够的重叠余量;以及使用上述制造的半导体器件方法。该器件包括形成在元件隔离层上的栅电极，它们设置在有源区之间并具有高于有源区顶表面的顶表面。由于栅电极形成在元件隔离层上，所以防止了半导体衬底中的漏电流。此外，使用条纹形掩模图案形成栅电极，从而与接触形状或条形图案相比获得足够的重叠余量。

6. 发明授权

US08563373B2 Semiconductor device having vertical channels and method of manufacturing the same 有权
公开(公告)号：US08563373B2
公开(公告)日：2013-10-22
申请号：US12548219
申请日：2009-08-26
申请人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
发明人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
IPC分类号： H01L21/338
CPC分类号： H01L21/28123 , H01L21/76224 , H01L27/088 , H01L27/0886 , H01L27/10826 , H01L27/10879 , H01L29/0649 , H01L29/0653 , H01L29/4238 , H01L29/66795 , H01L29/7802 , H01L29/7827 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

7. 发明申请

US20090114967A1 TRANSISTORS HAVING A CHANNEL REGION BETWEEN CHANNEL-PORTION HOLES AND METHODS OF FORMING THE SAME 失效
标题翻译：在通道孔之间具有通道区域的晶体管及其形成方法
公开(公告)号：US20090114967A1
公开(公告)日：2009-05-07
申请号：US12345415
申请日：2008-12-29
申请人： Jin-Woo Lee , Tae-Young Chung , Yong-Sung Kim
发明人： Jin-Woo Lee , Tae-Young Chung , Yong-Sung Kim
IPC分类号： H01L27/108 , H01L49/00
CPC分类号： H01L29/66659 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L27/10823 , H01L27/10876 , H01L27/10888 , H01L29/66621 , H01L29/7834 , H01L29/7835
摘要： According to some embodiments of the invention, transistors have channel regions between channel-portion holes. Methods of forming the same include at least two channel-portion holes disposed in a semiconductor substrate. Line patterns are formed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate to fill the channel-portion holes. A channel region is disposed in the semiconductor substrate below the line patterns. At this time, the channel region is formed between the channel-portion holes and also covers lower portions of the channel-portion holes. Driving current capability and refresh characteristics of DRAMs utilizing the inventive transistors are improved.
摘要翻译：根据本发明的一些实施例，晶体管在沟道部分孔之间具有沟道区。形成它们的方法包括设置在半导体衬底中的至少两个通道部分孔。线图案平行地形成为在半导体衬底的主表面上彼此间隔开以填充沟道部分孔。沟道区域设置在半导体衬底中的线图案下方。此时，通道区域形成在通道部分孔之间并且还覆盖通道部分孔的下部。利用本发明晶体管驱动DRAM的驱动电流能力和刷新特性得到改善。

8. 发明授权

US08637934B2 Semiconductor device having vertical channels and method of manufacturing the same 有权
标题翻译：具有垂直通道的半导体器件及其制造方法
公开(公告)号：US08637934B2
公开(公告)日：2014-01-28
申请号：US13899911
申请日：2013-05-22
申请人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
发明人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
IPC分类号： H01L29/76
CPC分类号： H01L21/28123 , H01L21/76224 , H01L27/088 , H01L27/0886 , H01L27/10826 , H01L27/10879 , H01L29/0649 , H01L29/0653 , H01L29/4238 , H01L29/66795 , H01L29/7802 , H01L29/7827 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
摘要翻译：一种制造半导体器件的方法，该半导体器件能够防止由有源区的长轴与元件隔离层相交的栅电极引起的泄漏电流，并且还具有垂直沟道以提供足够的重叠余量;以及使用上述制造的半导体器件方法。该器件包括形成在元件隔离层上的栅电极，它们设置在有源区之间并具有高于有源区顶表面的顶表面。由于栅电极形成在元件隔离层上，所以防止了半导体衬底中的漏电流。此外，使用条纹形掩模图案形成栅电极，从而与接触形状或条形图案相比获得足够的重叠余量。

9. 发明授权

US08039895B2 Transistors having a channel region between channel-portion holes and methods of forming the same 失效
标题翻译：在通道部分孔之间具有沟道区的晶体管及其形成方法
公开(公告)号：US08039895B2
公开(公告)日：2011-10-18
申请号：US12345415
申请日：2008-12-29
申请人： Jin-Woo Lee , Tae-Young Chung , Yong-Sung Kim
发明人： Jin-Woo Lee , Tae-Young Chung , Yong-Sung Kim
IPC分类号： H01L29/76
CPC分类号： H01L29/66659 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L27/10823 , H01L27/10876 , H01L27/10888 , H01L29/66621 , H01L29/7834 , H01L29/7835
摘要： According to some embodiments of the invention, transistors have channel regions between channel-portion holes. Methods of forming the same include at least two channel-portion holes disposed in a semiconductor substrate. Line patterns are formed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate to fill the channel-portion holes. A channel region is disposed in the semiconductor substrate below the line patterns. At this time, the channel region is formed between the channel-portion holes and also covers lower portions of the channel-portion holes. Driving current capability and refresh characteristics of DRAMs utilizing the inventive transistors are improved.
摘要翻译：根据本发明的一些实施例，晶体管在沟道部分孔之间具有沟道区。形成它们的方法包括设置在半导体衬底中的至少两个通道部分孔。线图案平行地形成为在半导体衬底的主表面上彼此间隔开以填充沟道部分孔。沟道区域设置在半导体衬底中的线图案下方。此时，通道区域形成在通道部分孔之间并且还覆盖通道部分孔的下部。利用本发明晶体管驱动DRAM的驱动电流能力和刷新特性得到改善。

10. 发明授权

US07902607B2 Fabrication of local damascene finFETs using contact type nitride damascene mask 失效
标题翻译：使用接触式氮化物镶嵌掩模制造局部大马士革finFET
公开(公告)号：US07902607B2
公开(公告)日：2011-03-08
申请号：US12318238
申请日：2008-12-23
申请人： Yong-Sung Kim , Tae-Young Chung
发明人： Yong-Sung Kim , Tae-Young Chung
IPC分类号： H01L21/331
CPC分类号： H01L29/785 , H01L27/1211 , H01L29/66795
摘要： Disclosed are methods for forming FinFETs using a first hard mask pattern to define active regions and a second hard mask to protect portions of the insulating regions between active regions. The resulting field insulating structure has three distinct regions distinguished by the vertical offset from a reference plane defined by the surface of the active regions. These three regions will include a lower surface found in the recessed openings resulting from the damascene etch, an intermediate surface and an upper surface on the remaining portions of the lateral field insulating regions. The general correspondence between the reference plane and the intermediate surface will tend to suppress or eliminate residual gate electrode materials from this region during formation of the gate electrodes, thereby improving the electrical isolation between adjacent active regions and improving the performance of the resulting semiconductor devices.
摘要翻译：公开了使用第一硬掩模图案形成FinFET以限定有源区的方法和用于保护有源区之间绝缘区的部分的第二硬掩模的方法。所得到的场绝缘结构具有由与活性区域的表面限定的参考平面的垂直偏移区分的三个不同区域。这三个区域将包括由镶嵌蚀刻产生的凹入开口中的下表面，侧面场绝缘区域的其余部分上的中间表面和上表面。在形成栅电极期间，参考平面和中间表面之间的一般对应关系将倾向于抑制或消除该区域中的剩余栅电极材料，从而改善相邻有源区之间的电隔离并提高所得半导体器件的性能。

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