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1. 发明授权

US07413943B2 Method of fabricating gate of fin type transistor 有权
标题翻译：鳍型晶体管栅极的制造方法
公开(公告)号：US07413943B2
公开(公告)日：2008-08-19
申请号：US11460905
申请日：2006-07-28
申请人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
发明人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
IPC分类号： H01L21/336 , H01L31/062
CPC分类号： H01L21/823437 , H01L21/823412 , H01L29/66795 , H01L29/7851
摘要： A method of fabricating a gate of a fin type transistor includes forming hard masks to define active regions of a substrate. A shallow trench isolation method is performed to form a first device separation layer, and then an etch-back process is performed such that the active regions protrude. Sidewall protection layers are formed on sidewalls of the active region, and a second device separation layer is formed thereon, thereby obtaining a device isolation region. The sidewall protection layers include an insulation material with an etch selectivity with respect to an insulation material composing the device isolation region. The device isolation region is selectively etched to form recesses for a fin type active region. Dry etching and wet etching are performed on the silicon nitride to remove the hard masks and the sidewall protection layers, respectively. Gates are formed to fill the recesses.
摘要翻译：制造鳍式晶体管的栅极的方法包括形成硬掩模以限定衬底的有源区。执行浅沟槽隔离方法以形成第一器件分离层，然后执行回蚀处理，使得有源区域突出。侧壁保护层形成在有源区的侧壁上，并且在其上形成第二器件分离层，从而获得器件隔离区。侧壁保护层包括相对于构成器件隔离区域的绝缘材料具有蚀刻选择性的绝缘材料。选择性地蚀刻器件隔离区以形成翅片型有源区的凹槽。对氮化硅进行干蚀刻和湿蚀刻以分别去除硬掩模和侧壁保护层。形成门以填充凹部。

2. 发明申请

US20140103482A1 SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNELS AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：具有垂直通道的半导体器件及其制造方法
公开(公告)号：US20140103482A1
公开(公告)日：2014-04-17
申请号：US14109517
申请日：2013-12-17
申请人： Yong-Sung Kim , Tae-Young CHUNG , Soo-Ho SHIN
发明人： Yong-Sung Kim , Tae-Young CHUNG , Soo-Ho SHIN
IPC分类号： H01L29/06 , H01L27/088
CPC分类号： H01L21/28123 , H01L21/76224 , H01L27/088 , H01L27/0886 , H01L27/10826 , H01L27/10879 , H01L29/0649 , H01L29/0653 , H01L29/4238 , H01L29/66795 , H01L29/7802 , H01L29/7827 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
摘要翻译：一种制造半导体器件的方法，该半导体器件能够防止由有源区的长轴与元件隔离层相交的栅电极引起的泄漏电流，并且还具有垂直沟道以提供足够的重叠余量;以及使用上述制造的半导体器件方法。该器件包括形成在元件隔离层上的栅电极，它们设置在有源区之间并具有高于有源区顶表面的顶表面。由于栅电极形成在元件隔离层上，所以防止了半导体衬底中的漏电流。此外，使用条纹形掩模图案形成栅电极，从而与接触形状或条形图案相比获得足够的重叠余量。

3. 发明授权

US08563373B2 Semiconductor device having vertical channels and method of manufacturing the same 有权
公开(公告)号：US08563373B2
公开(公告)日：2013-10-22
申请号：US12548219
申请日：2009-08-26
申请人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
发明人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
IPC分类号： H01L21/338
CPC分类号： H01L21/28123 , H01L21/76224 , H01L27/088 , H01L27/0886 , H01L27/10826 , H01L27/10879 , H01L29/0649 , H01L29/0653 , H01L29/4238 , H01L29/66795 , H01L29/7802 , H01L29/7827 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

4. 发明授权

US08637934B2 Semiconductor device having vertical channels and method of manufacturing the same 有权
标题翻译：具有垂直通道的半导体器件及其制造方法
公开(公告)号：US08637934B2
公开(公告)日：2014-01-28
申请号：US13899911
申请日：2013-05-22
申请人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
发明人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
IPC分类号： H01L29/76
CPC分类号： H01L21/28123 , H01L21/76224 , H01L27/088 , H01L27/0886 , H01L27/10826 , H01L27/10879 , H01L29/0649 , H01L29/0653 , H01L29/4238 , H01L29/66795 , H01L29/7802 , H01L29/7827 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
摘要翻译：一种制造半导体器件的方法，该半导体器件能够防止由有源区的长轴与元件隔离层相交的栅电极引起的泄漏电流，并且还具有垂直沟道以提供足够的重叠余量;以及使用上述制造的半导体器件方法。该器件包括形成在元件隔离层上的栅电极，它们设置在有源区之间并具有高于有源区顶表面的顶表面。由于栅电极形成在元件隔离层上，所以防止了半导体衬底中的漏电流。此外，使用条纹形掩模图案形成栅电极，从而与接触形状或条形图案相比获得足够的重叠余量。

5. 发明申请

US20100248437A1 Methods of forming recessed gate structures including blocking members, and methods of forming semiconductor devices having the recessed gate structures 失效
标题翻译：形成包括阻挡构件的凹陷栅极结构的方法，以及形成具有凹陷栅极结构的半导体器件的方法
公开(公告)号：US20100248437A1
公开(公告)日：2010-09-30
申请号：US12784977
申请日：2010-05-21
申请人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin , Eun-Cheol Lee
发明人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin , Eun-Cheol Lee
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/4236 , H01L29/4925 , H01L29/4933 , H01L29/4941 , H01L29/66621
摘要： A recessed gate structure in a semiconductor device includes a gate electrode partially buried in a substrate, a blocking member formed in the buried portion of the gate electrode, and a gate insulation layer formed between the gate electrode and the substrate. The blocking member may effectively prevent a void or a seam in the buried portion of the gate electrode from contacting the gate insulation layer adjacent to a channel region in subsequent manufacturing processes. Thus, the semiconductor device may have a regular threshold voltage and a leakage current passing through the void or the seam may efficiently decrease.
摘要翻译：半导体器件中的凹陷栅极结构包括部分地埋在衬底中的栅电极，形成在栅极的掩埋部分中的阻挡构件以及形成在栅电极和衬底之间的栅极绝缘层。阻挡构件可以有效地防止栅极电极的掩埋部分中的空隙或接缝在随后的制造工艺中接触与沟道区域相邻的栅极绝缘层。因此，半导体器件可以具有规则的阈值电压，并且通过空隙或接缝的漏电流可以有效地降低。

6. 发明申请

US20070023791A1 METHOD OF FABRICATING GATE OF FIN TYPE TRANSISTOR 有权
标题翻译： FIN型晶体管的制造方法
公开(公告)号：US20070023791A1
公开(公告)日：2007-02-01
申请号：US11460905
申请日：2006-07-28
申请人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
发明人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
IPC分类号： H01L21/8234
CPC分类号： H01L21/823437 , H01L21/823412 , H01L29/66795 , H01L29/7851
摘要： A method of fabricating a gate of a fin type transistor includes forming hard masks to define active regions of a substrate. A shallow trench isolation method is performed to form a first device separation layer, and then an etch-back process is performed such that the active regions protrude. Sidewall protection layers are formed on sidewalls of the active region, and a second device separation layer is formed thereon, thereby obtaining a device isolation region. The sidewall protection layers include an insulation material with an etch selectivity with respect to an insulation material composing the device isolation region. The device isolation region is selectively etched to form recesses for a fin type active region. Dry etching and wet etching are performed on the silicon nitride to remove the hard masks and the sidewall protection layers, respectively. Gates are formed to fill the recesses.
摘要翻译：制造鳍式晶体管的栅极的方法包括形成硬掩模以限定衬底的有源区。执行浅沟槽隔离方法以形成第一器件分离层，然后执行回蚀处理，使得有源区域突出。侧壁保护层形成在有源区的侧壁上，并且在其上形成第二器件分离层，从而获得器件隔离区。侧壁保护层包括相对于构成器件隔离区域的绝缘材料具有蚀刻选择性的绝缘材料。选择性地蚀刻器件隔离区以形成翅片型有源区的凹槽。对氮化硅进行干蚀刻和湿蚀刻以分别去除硬掩模和侧壁保护层。形成门以填充凹部。

7. 发明申请

US20130248984A1 SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNELS AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20130248984A1
公开(公告)日：2013-09-26
申请号：US13899911
申请日：2013-05-22
申请人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
发明人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
IPC分类号： H01L29/78 , H01L27/088
CPC分类号： H01L21/28123 , H01L21/76224 , H01L27/088 , H01L27/0886 , H01L27/10826 , H01L27/10879 , H01L29/0649 , H01L29/0653 , H01L29/4238 , H01L29/66795 , H01L29/7802 , H01L29/7827 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

8. 发明授权

US08183113B2 Methods of forming recessed gate structures including blocking members, and methods of forming semiconductor devices having the recessed gate structures 失效
标题翻译：形成包括阻挡构件的凹陷栅极结构的方法，以及形成具有凹陷栅极结构的半导体器件的方法
公开(公告)号：US08183113B2
公开(公告)日：2012-05-22
申请号：US12784977
申请日：2010-05-21
申请人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin , Eun-Cheol Lee
发明人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin , Eun-Cheol Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/4236 , H01L29/4925 , H01L29/4933 , H01L29/4941 , H01L29/66621
摘要： A recessed gate structure in a semiconductor device includes a gate electrode partially buried in a substrate, a blocking member formed in the buried portion of the gate electrode, and a gate insulation layer formed between the gate electrode and the substrate. The blocking member may effectively prevent a void or a seam in the buried portion of the gate electrode from contacting the gate insulation layer adjacent to a channel region in subsequent manufacturing processes. Thus, the semiconductor device may have a regular threshold voltage and a leakage current passing through the void or the seam may efficiently decrease.
摘要翻译：半导体器件中的凹陷栅极结构包括部分地埋在衬底中的栅电极，形成在栅极的掩埋部分中的阻挡构件以及形成在栅电极和衬底之间的栅极绝缘层。阻挡构件可以有效地防止栅极电极的掩埋部分中的空隙或接缝在随后的制造工艺中接触与沟道区域相邻的栅极绝缘层。因此，半导体器件可以具有规则的阈值电压，并且通过空隙或接缝的漏电流可以有效地降低。

9. 发明申请

US20060289931A1 Recessed gate structures including blocking members, methods of forming the same, semiconductor devices having the recessed gate structures and methods of forming the semiconductor devices 审中-公开
标题翻译：包括阻挡构件的嵌入栅极结构，其形成方法，具有凹陷栅结构的半导体器件和形成半导体器件的方法
公开(公告)号：US20060289931A1
公开(公告)日：2006-12-28
申请号：US11507753
申请日：2006-08-22
申请人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin , Eun-Cheol Lee
发明人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin , Eun-Cheol Lee
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/945 , H01L21/7624 , H01L29/4236 , H01L29/66181 , H01L29/66621 , H01L29/7834
摘要： A recessed gate structure in a semiconductor device includes a gate electrode partially buried in a substrate, a blocking member formed in the buried portion of the gate electrode, and a gate insulation layer formed between the gate electrode and the substrate. The blocking member may effectively prevent a void or a seam in the buried portion of the gate electrode from contacting the gate insulation layer adjacent to a channel region in subsequent manufacturing processes. Thus, the semiconductor device may have a regular threshold voltage and a leakage current passing through the void or the seam may efficiently decrease.
摘要翻译：半导体器件中的凹陷栅极结构包括部分地埋在衬底中的栅电极，形成在栅极的掩埋部分中的阻挡构件以及形成在栅电极和衬底之间的栅极绝缘层。阻挡构件可以有效地防止栅极电极的掩埋部分中的空隙或接缝在随后的制造工艺中接触与沟道区域相邻的栅极绝缘层。因此，半导体器件可以具有规则的阈值电压，并且通过空隙或接缝的漏电流可以有效地降低。

10. 发明授权

US07598571B2 Semiconductor device having vertical channels and method of manufacturing the same 有权
标题翻译：具有垂直通道的半导体器件及其制造方法
公开(公告)号：US07598571B2
公开(公告)日：2009-10-06
申请号：US11457781
申请日：2006-07-14
申请人： Yong-Sung Kim , Tae-Yong Chung , Soo-Ho Shin
发明人： Yong-Sung Kim , Tae-Yong Chung , Soo-Ho Shin
IPC分类号： H01L29/76
CPC分类号： H01L21/28123 , H01L21/76224 , H01L27/088 , H01L27/0886 , H01L27/10826 , H01L27/10879 , H01L29/0649 , H01L29/0653 , H01L29/4238 , H01L29/66795 , H01L29/7802 , H01L29/7827 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
摘要翻译：一种制造半导体器件的方法，该半导体器件能够防止由有源区的长轴与元件隔离层相交的栅电极引起的泄漏电流，并且还具有垂直沟道以提供足够的重叠余量;以及使用上述制造的半导体器件方法。该器件包括形成在元件隔离层上的栅电极，它们设置在有源区之间并具有高于有源区顶表面的顶表面。由于栅电极形成在元件隔离层上，所以防止了半导体衬底中的漏电流。此外，使用条纹形掩模图案形成栅电极，从而与接触形状或条形图案相比获得足够的重叠余量。

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