专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060049445A1 Dram having at least three layered impurity regions between channel holes and method of fabricating same 失效
标题翻译：在通道孔之间具有至少三层杂质区和其制造方法
公开(公告)号：US20060049445A1
公开(公告)日：2006-03-09
申请号：US11210705
申请日：2005-08-25
申请人： Jin-Woo Lee , Yong-Sung Kim , Tae-Young Chung
发明人： Jin-Woo Lee , Yong-Sung Kim , Tae-Young Chung
IPC分类号： H01L27/108
CPC分类号： H01L29/0847 , H01L21/76895 , H01L27/10852 , H01L27/10876 , H01L27/10888 , H01L29/66621 , H01L29/66659
摘要： Disclosed is a dynamic random access memory (DRAM) comprising a transistor having channel holes formed in the channel region thereof and cell gate structures formed in the channel holes. At least three layered impurity regions are formed in a semiconductor substrate between the channel holes and the at least three layered impurity regions form a source region for the transistor.
摘要翻译：公开了一种动态随机存取存储器（DRAM），其包括晶体管，该晶体管具有在其沟道区中形成的沟道孔，并且形成在沟道孔中的单元栅极结构。在通道孔和至少三层杂质区之间的半导体衬底中形成至少三层杂质区，形成晶体管的源极区。

2. 发明申请

US20090114967A1 TRANSISTORS HAVING A CHANNEL REGION BETWEEN CHANNEL-PORTION HOLES AND METHODS OF FORMING THE SAME 失效
标题翻译：在通道孔之间具有通道区域的晶体管及其形成方法
公开(公告)号：US20090114967A1
公开(公告)日：2009-05-07
申请号：US12345415
申请日：2008-12-29
申请人： Jin-Woo Lee , Tae-Young Chung , Yong-Sung Kim
发明人： Jin-Woo Lee , Tae-Young Chung , Yong-Sung Kim
IPC分类号： H01L27/108 , H01L49/00
CPC分类号： H01L29/66659 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L27/10823 , H01L27/10876 , H01L27/10888 , H01L29/66621 , H01L29/7834 , H01L29/7835
摘要： According to some embodiments of the invention, transistors have channel regions between channel-portion holes. Methods of forming the same include at least two channel-portion holes disposed in a semiconductor substrate. Line patterns are formed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate to fill the channel-portion holes. A channel region is disposed in the semiconductor substrate below the line patterns. At this time, the channel region is formed between the channel-portion holes and also covers lower portions of the channel-portion holes. Driving current capability and refresh characteristics of DRAMs utilizing the inventive transistors are improved.
摘要翻译：根据本发明的一些实施例，晶体管在沟道部分孔之间具有沟道区。形成它们的方法包括设置在半导体衬底中的至少两个通道部分孔。线图案平行地形成为在半导体衬底的主表面上彼此间隔开以填充沟道部分孔。沟道区域设置在半导体衬底中的线图案下方。此时，通道区域形成在通道部分孔之间并且还覆盖通道部分孔的下部。利用本发明晶体管驱动DRAM的驱动电流能力和刷新特性得到改善。

3. 发明申请

US20050179075A1 Transistors having a channel region between channel-portion holes and methods of forming the same 失效
标题翻译：在通道部分孔之间具有沟道区的晶体管及其形成方法
公开(公告)号：US20050179075A1
公开(公告)日：2005-08-18
申请号：US11054104
申请日：2005-02-08
申请人： Jin-Woo Lee , Tae-Young Chung , Yong-Sung Kim
发明人： Jin-Woo Lee , Tae-Young Chung , Yong-Sung Kim
IPC分类号： H01L21/20 , H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/78 , H01L31/119
CPC分类号： H01L29/66659 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L27/10823 , H01L27/10876 , H01L27/10888 , H01L29/66621 , H01L29/7834 , H01L29/7835
摘要： According to some embodiments of the invention, transistors have channel regions between channel-portion holes. Methods of forming the same include at least two channel-portion holes disposed in a semiconductor substrate. Line patterns are formed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate to fill the channel-portion holes. A channel region is disposed in the semiconductor substrate below the line patterns. At this time, the channel region is formed between the channel-portion holes and also covers lower portions of the channel-portion holes. Driving current capability and refresh characteristics of DRAMs utilizing the inventive transistors are improved.
摘要翻译：根据本发明的一些实施例，晶体管在沟道部分孔之间具有沟道区。形成它们的方法包括设置在半导体衬底中的至少两个通道部分孔。线图案平行地形成为在半导体衬底的主表面上彼此间隔开以填充沟道部分孔。沟道区域设置在半导体衬底中的线图案下方。此时，通道区域形成在通道部分孔之间并且还覆盖通道部分孔的下部。利用本发明晶体管驱动DRAM的驱动电流能力和刷新特性得到改善。

4. 发明授权

US07368778B2 DRAM having at least three layered impurity regions between channel holes and method of fabricating same 失效
标题翻译：在通道孔之间具有至少三层杂质区的DRAM及其制造方法
公开(公告)号：US07368778B2
公开(公告)日：2008-05-06
申请号：US11210705
申请日：2005-08-25
申请人： Jin-Woo Lee , Yong-Sung Kim , Tae-Young Chung
发明人： Jin-Woo Lee , Yong-Sung Kim , Tae-Young Chung
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/0847 , H01L21/76895 , H01L27/10852 , H01L27/10876 , H01L27/10888 , H01L29/66621 , H01L29/66659
摘要： Disclosed is a dynamic random access memory (DRAM) comprising a transistor having channel holes formed in the channel region thereof and cell gate structures formed in the channel holes. At least three layered impurity regions are formed in a semiconductor substrate between the channel holes and the at least three layered impurity regions form a source region for the transistor.
摘要翻译：公开了一种动态随机存取存储器（DRAM），其包括晶体管，该晶体管具有在其沟道区中形成的沟道孔，并且形成在沟道孔中的单元栅极结构。在通道孔和至少三层杂质区之间的半导体衬底中形成至少三层杂质区，形成晶体管的源极区。

5. 发明授权

US08039895B2 Transistors having a channel region between channel-portion holes and methods of forming the same 失效
标题翻译：在通道部分孔之间具有沟道区的晶体管及其形成方法
公开(公告)号：US08039895B2
公开(公告)日：2011-10-18
申请号：US12345415
申请日：2008-12-29
申请人： Jin-Woo Lee , Tae-Young Chung , Yong-Sung Kim
发明人： Jin-Woo Lee , Tae-Young Chung , Yong-Sung Kim
IPC分类号： H01L29/76
CPC分类号： H01L29/66659 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L27/10823 , H01L27/10876 , H01L27/10888 , H01L29/66621 , H01L29/7834 , H01L29/7835
摘要： According to some embodiments of the invention, transistors have channel regions between channel-portion holes. Methods of forming the same include at least two channel-portion holes disposed in a semiconductor substrate. Line patterns are formed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate to fill the channel-portion holes. A channel region is disposed in the semiconductor substrate below the line patterns. At this time, the channel region is formed between the channel-portion holes and also covers lower portions of the channel-portion holes. Driving current capability and refresh characteristics of DRAMs utilizing the inventive transistors are improved.
摘要翻译：根据本发明的一些实施例，晶体管在沟道部分孔之间具有沟道区。形成它们的方法包括设置在半导体衬底中的至少两个通道部分孔。线图案平行地形成为在半导体衬底的主表面上彼此间隔开以填充沟道部分孔。沟道区域设置在半导体衬底中的线图案下方。此时，通道区域形成在通道部分孔之间并且还覆盖通道部分孔的下部。利用本发明晶体管驱动DRAM的驱动电流能力和刷新特性得到改善。

6. 发明授权

US07492004B2 Transistors having a channel region between channel-portion holes and methods of forming the same 失效
标题翻译：在通道部分孔之间具有沟道区的晶体管及其形成方法
公开(公告)号：US07492004B2
公开(公告)日：2009-02-17
申请号：US11054104
申请日：2005-02-08
申请人： Jin-Woo Lee , Tae-Young Chung , Yong-Sung Kim
发明人： Jin-Woo Lee , Tae-Young Chung , Yong-Sung Kim
IPC分类号： H01L29/94
CPC分类号： H01L29/66659 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L27/10823 , H01L27/10876 , H01L27/10888 , H01L29/66621 , H01L29/7834 , H01L29/7835
摘要： According to some embodiments of the invention, transistors have channel regions between channel-portion holes. Methods of forming the same include at least two channel-portion holes disposed in a semiconductor substrate. Line patterns are formed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate to fill the channel-portion holes. A channel region is disposed in the semiconductor substrate below the line patterns. At this time, the channel region is formed between the channel-portion holes and also covers lower portions of the channel-portion holes. Driving current capability and refresh characteristics of DRAMs utilizing the inventive transistors are improved.
摘要翻译：根据本发明的一些实施例，晶体管在沟道部分孔之间具有沟道区。形成它们的方法包括设置在半导体衬底中的至少两个通道部分孔。线图案平行地形成为在半导体衬底的主表面上彼此间隔开以填充沟道部分孔。沟道区域设置在半导体衬底中的线图案下方。此时，通道区域形成在通道部分孔之间并且还覆盖通道部分孔的下部。利用本发明晶体管驱动DRAM的驱动电流能力和刷新特性得到改善。

7. 发明申请

US20080001230A1 Semiconductor devices including transistors having recessed channels and methods of fabricating the same 失效
标题翻译：包括具有凹陷通道的晶体管的半导体器件及其制造方法
公开(公告)号：US20080001230A1
公开(公告)日：2008-01-03
申请号：US11704872
申请日：2007-02-09
申请人： Jin-Woo Lee , Tae-Young Chung , Sung-Hee Han
发明人： Jin-Woo Lee , Tae-Young Chung , Sung-Hee Han
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L21/823437 , H01L21/823481 , H01L29/4236 , H01L29/42376 , H01L29/66621
摘要： Semiconductor devices including an isolation layer on a semiconductor substrate are provided. The isolation layer defines an active region of the semiconductor substrate. The device further includes an upper gate electrode crossing over the active region and extending to the isolation layer and lower active gate electrode. The lower active gate electrode includes a first active gate electrode extending from the upper gate electrode to the active region and a second active gate electrode below the first active gate electrode and having a greater width than a width of the first active gate electrode. The device further includes a lower field gate electrode that extends from the upper gate electrode to the isolation layer and has a bottom surface that is at a lower level than a bottom surface of the active gate electrode such that the sidewalls of the active region are covered below the lower active gate electrode. Related methods of fabricating semiconductor devices are also provided herein.
摘要翻译：提供包括半导体衬底上的隔离层的半导体器件。隔离层限定半导体衬底的有源区。该器件还包括与有源区交叉并延伸到隔离层和下活性栅电极的上栅电极。下有源栅电极包括从上栅极延伸到有源区的第一有源栅电极和位于第一有源栅电极下方并且具有比第一有源栅电极的宽度更大的宽度的第二有源栅电极。该器件还包括一个从上部栅电极延伸到隔离层的下部栅极电极，并且具有一底部表面，该底表面处于与该有源栅极电极的底表面相比较低的位置，使得该有源区域的侧壁被覆盖在下部有源栅电极下方。本文还提供了制造半导体器件的相关方法。

8. 发明授权

US07893487B2 Recessed channel transistor 失效
标题翻译：嵌入式沟道晶体管
公开(公告)号：US07893487B2
公开(公告)日：2011-02-22
申请号：US12314582
申请日：2008-12-12
申请人： Jin-Woo Lee , Tae-Young Chung , Joo-Young Lee
发明人： Jin-Woo Lee , Tae-Young Chung , Joo-Young Lee
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66621 , H01L21/26513 , H01L21/823412 , H01L21/823437 , H01L29/1037 , H01L29/105 , H01L29/4236
摘要： A recessed channel transistor includes a single crystalline silicon substrate having a recessed portion, a bottom surface of the recessed portion including an elevated central portion, a channel doping region in the single crystalline silicon substrate, the channel doping region being under the bottom surface of the recessed portion, a gate structure in the recessed portion, and source/drain regions in the single crystalline silicon substrate at both sides of the recessed portion, the source/drain regions being spaced apart from the bottom surface of the recessed portion.
摘要翻译：凹陷沟道晶体管包括具有凹陷部分的单晶硅衬底，凹部的底表面包括升高的中心部分，在单晶硅衬底中的沟道掺杂区域，沟道掺杂区域位于凹陷部分，凹陷部分中的栅极结构以及在凹陷部分两侧的单晶硅衬底中的源极/漏极区域，源极/漏极区域与凹陷部分的底表面间隔开。

9. 发明授权

US07666743B2 Methods of fabricating semiconductor devices including transistors having recessed channels 失效
标题翻译：制造包括具有凹槽的晶体管的半导体器件的方法
公开(公告)号：US07666743B2
公开(公告)日：2010-02-23
申请号：US11704872
申请日：2007-02-09
申请人： Jin-Woo Lee , Tae-Young Chung , Sung-Hee Han
发明人： Jin-Woo Lee , Tae-Young Chung , Sung-Hee Han
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/823437 , H01L21/823481 , H01L29/4236 , H01L29/42376 , H01L29/66621
摘要： Semiconductor devices including an isolation layer on a semiconductor substrate are provided. The isolation layer defines an active region of the semiconductor substrate. The device further includes an upper gate electrode crossing over the active region and extending to the isolation layer and lower active gate electrode. The lower active gate electrode includes a first active gate electrode extending from the upper gate electrode to the active region and a second active gate electrode below the first active gate electrode and having a greater width than a width of the first active gate electrode. The device further includes a lower field gate electrode that extends from the upper gate electrode to the isolation layer and has a bottom surface that is at a lower level than a bottom surface of the active gate electrode such that the sidewalls of the active region are covered below the lower active gate electrode. Related methods of fabricating semiconductor devices are also provided herein.
摘要翻译：提供包括半导体衬底上的隔离层的半导体器件。隔离层限定了半导体衬底的有源区。该器件还包括与有源区交叉并延伸到隔离层和下活性栅电极的上栅电极。下有源栅电极包括从上栅极延伸到有源区的第一有源栅电极和位于第一有源栅电极下方并且具有比第一有源栅电极的宽度更大的宽度的第二有源栅电极。该器件还包括一个从上部栅电极延伸到隔离层的下部栅极电极，并且具有一底部表面，该底表面处于与该有源栅极电极的底表面相比较低的位置，使得该有源区域的侧壁被覆盖在下部有源栅电极下方。本文还提供了制造半导体器件的相关方法。

10. 发明授权

US07923331B2 Method of fabricating recess channel transistor having locally thick dielectrics and related devices 有权
标题翻译：制造具有局部厚电介质和相关器件的凹槽沟道晶体管的方法
公开(公告)号：US07923331B2
公开(公告)日：2011-04-12
申请号：US12232020
申请日：2008-09-10
申请人： Sung-Hee Han , Jin-Woo Lee , Tae-Young Chung , Ja-Young Lee
发明人： Sung-Hee Han , Jin-Woo Lee , Tae-Young Chung , Ja-Young Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/3247 , H01L29/1037 , H01L29/42376 , H01L29/66553 , H01L29/66621 , H01L29/78
摘要： Provided are a method of fabricating a recess channel transistor and a related semiconductor device. The method may include forming a first gate trench on a substrate, forming a dielectric spacer on a sidewall of the first gate trench, forming a second gate trench on the substrate under the first gate trench, and forming a gate electrode to fill the trenches. The dielectric spacer may remain between the gate electrode and the substrate.
摘要翻译：提供一种制造凹槽通道晶体管和相关半导体器件的方法。该方法可以包括在衬底上形成第一栅极沟槽，在第一栅极沟槽的侧壁上形成电介质间隔物，在第一栅极沟槽下面的衬底上形成第二栅极沟槽，以及形成栅电极以填充沟槽。电介质隔离物可以保留在栅电极和衬底之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式