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1. 发明授权

US07659174B2 Method to enhance device performance with selective stress relief 有权
标题翻译：通过选择性应力消除来增强设备性能的方法
公开(公告)号：US07659174B2
公开(公告)日：2010-02-09
申请号：US11930230
申请日：2007-10-31
申请人： Yong Meng Lee , Haining S. Yang , Victor Chan
发明人： Yong Meng Lee , Haining S. Yang , Victor Chan
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.
摘要翻译：在衬底的一个区域中的应力层下方具有应力消除层的半导体器件的制造结构和方法。在第一示例中，应力消除层形成在衬底的第一区域（例如，PFET区域）上，而不是在第二区域（例如，NFET区域）之上。应力层在第一区域中的应力消除层上方和第二区域中的器件和衬底/硅化物之上。 NFET晶体管的性能由于NFET沟道中的整体拉伸应力而增强，而由于包含应力消除层而降低/消除了PFET晶体管性能的降低。在第二示例性实施例中，应力消除层形成在第二区域上，但不是第一区域并且应力层的应力被反转。

2. 发明申请

US20080026523A1 Structure and method to implement dual stressor layers with improved silicide control 审中-公开
标题翻译：具有改进的硅化物控制的双应力层的结构和方法
公开(公告)号：US20080026523A1
公开(公告)日：2008-01-31
申请号：US11495508
申请日：2006-07-28
申请人： Yong Meng Lee , Haining S. Yang , Victor Chan , Eng Hua Lim
发明人： Yong Meng Lee , Haining S. Yang , Victor Chan , Eng Hua Lim
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823835 , H01L21/823864 , H01L29/7843
摘要： An example embodiment for a method of fabrication of a semiconductor device comprises the following. We provide a substrate with a first device region and a second device region. We provide a first type FET transistor in the first device region and provide a second type FET transistor in the second device region. We form an etch stop layer over the first and second device regions and forming a first stressor layer over the first device region. The first stressor layer puts a first type stress on the substrate in the first device region. We form a second stressor layer over the second device region. The second stressor layer puts a second type stress on the substrate in the second device region. Another example embodiment is the structure of a dual stress layer device having an etch stop layer.
摘要翻译：用于制造半导体器件的方法的示例实施例包括以下。我们提供具有第一器件区域和第二器件区域的衬底。我们在第一器件区域提供第一类型FET晶体管，并在第二器件区域中提供第二类型FET晶体管。我们在第一和第二器件区域上形成蚀刻停止层，并在第一器件区域上形成第一应激源层。第一应力层在第一器件区域中的衬底上施加第一类应力。我们在第二设备区域上形成第二应力层。第二应力层在第二器件区域中的衬底上施加第二类应力。另一示例性实施例是具有蚀刻停止层的双应力层器件的结构。

3. 发明申请

US20080050868A1 METHOD TO ENHANCE DEVICE PERFORMANCE WITH SELECTIVE STRESS RELIEF 有权
标题翻译：增强选择性应力消除装置性能的方法
公开(公告)号：US20080050868A1
公开(公告)日：2008-02-28
申请号：US11930230
申请日：2007-10-31
申请人： Yong Meng Lee , Haining S. Yang , Victor Chan
发明人： Yong Meng Lee , Haining S. Yang , Victor Chan
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.
摘要翻译：在衬底的一个区域中的应力层下方具有应力消除层的半导体器件的制造结构和方法。在第一示例中，应力消除层形成在衬底的第一区域（例如，PFET区域）上，而不是在第二区域（例如，NFET区域）之上。应力层在第一区域中的应力消除层上方和第二区域中的器件和衬底/硅化物之上。 NFET晶体管的性能由于NFET沟道中的整体拉伸应力而增强，而由于包含应力消除层而降低/消除了PFET晶体管性能的降低。在第二示例性实施例中，应力消除层形成在第二区域上，但不是第一区域并且应力层的应力被反转。

4. 发明授权

US07309637B2 Method to enhance device performance with selective stress relief 有权
公开(公告)号：US07309637B2
公开(公告)日：2007-12-18
申请号：US11299542
申请日：2005-12-12
申请人： Yong Meng Lee , Haining S. Yang , Victor Chan
发明人： Yong Meng Lee , Haining S. Yang , Victor Chan
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.

5. 发明授权

US07396724B2 Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals 失效
标题翻译：双重混合衬垫形成，不将硅化物层暴露于光刻胶剥离化学品
公开(公告)号：US07396724B2
公开(公告)日：2008-07-08
申请号：US10907415
申请日：2005-03-31
申请人： Victor Chan , Haining S. Yang , Yong M. Lee , Eng H. Lim
发明人： Victor Chan , Haining S. Yang , Yong M. Lee , Eng H. Lim
IPC分类号： H01L21/8234
CPC分类号： H01L29/7843 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L29/665 , H01L29/66575 , H01L29/78
摘要： Methods of fabricating a semiconductor device including a dual-hybrid liner in which an underlying silicide layer is protected from photoresist stripping chemicals by using a hard mask as a pattern during etching, rather than using a photoresist. The hard mask prevents exposure of a silicide layer to photoresist stripping chemicals and provides very good lateral dimension control such that the two nitride liners are well aligned.
摘要翻译：制造包括双重混合衬垫的半导体器件的方法，其中通过在蚀刻期间使用硬掩模作为图案来保护底层硅化物层免受光致抗蚀剂剥离化学品，而不是使用光致抗蚀剂。硬掩模防止硅化物层暴露于光致抗蚀剂剥离化学品，并提供非常好的横向尺寸控制，使得两个氮化物衬垫良好对准。

6. 发明授权

US08562606B2 Ankle fusion device, instrumentation and methods 有权
标题翻译：脚踝融合装置，仪器和方法
公开(公告)号：US08562606B2
公开(公告)日：2013-10-22
申请号：US12965691
申请日：2010-12-10
申请人： Martinus Richter , Michael Pinzur , James DeOrio , Oliver Frick , Christophe Geisert , Thomas Loring , Stephen Gilbert , Victor Chan
发明人： Martinus Richter , Michael Pinzur , James DeOrio , Oliver Frick , Christophe Geisert , Thomas Loring , Stephen Gilbert , Victor Chan
IPC分类号： A61B17/56
CPC分类号： A61B17/8897 , A61B17/1642 , A61B17/1682 , A61B17/1697 , A61B17/1703 , A61B17/1717 , A61B17/1725 , A61B17/1775 , A61B17/7225 , A61B17/7291 , A61B17/86 , A61B17/8875 , A61B17/921 , A61B2090/3983
摘要： An ankle fusion device has a proximal portion generally aligned with a first longitudinal axis. The proximal portion includes a proximal end and a first fastener hole. The proximal portion has an arcuate curve such that the proximal end is spaced a distance from the first longitudinal axis in a first direction. The first fastener hole is configured to receive a first fastener along a first fastener axis. A distal portion of the ankle fusion device extends to a distal end from the proximal portion along a second longitudinal axis. The second longitudinal axis is angled in second and third directions relative to the first longitudinal axis. The second direction is perpendicular to the first direction and the third direction being opposite the first direction. The distal portion includes a second fastener hole configured to receive a second fastener along a second fastener axis.
摘要翻译：脚踝融合装置具有大致与第一纵向轴线对齐的近端部分。近端部分包括近端和第一紧固件孔。近端部分具有弓形曲线，使得近端在第一方向上与第一纵向轴线间隔开一定距离。第一紧固件孔构造成沿着第一紧固件轴线接收第一紧固件。脚踝融合装置的远端部分沿着第二纵向轴线从近端部分延伸到远端。第二纵向轴线相对于第一纵向轴线在第二和第三方向成角度。第二方向垂直于第一方向，第三方向与第一方向相反。远端部分包括第二紧固件孔，该第二紧固件孔构造成沿着第二紧固件轴线容纳第二紧固件。

7. 发明申请

US20120104511A1 DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS 有权
标题翻译： CMOS混合方向的双路隔离
公开(公告)号：US20120104511A1
公开(公告)日：2012-05-03
申请号：US13349203
申请日：2012-01-12
申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
发明人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
IPC分类号： H01L27/092
CPC分类号： H01L21/76229
摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
摘要翻译：本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第第一深度用于隔离相同极性的设备。本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

8. 发明申请

US20120089051A1 Blood Glucose Meter Having Integral Lancet Device And Test Strip Storage Vial For Single Handed Use And Methods For Using Same 有权
标题翻译：具有整体柳叶刀装置的血糖仪和用于单手使用的测试条储存瓶和使用相同的方法
公开(公告)号：US20120089051A1
公开(公告)日：2012-04-12
申请号：US13330330
申请日：2011-12-19
申请人： Gregg R. Draudt , Dirk Ahlgrim , Jan Schminke , Mark Follman , José Colucci, JR. , Raymond Yao , Robert J. McCaffrey , Victor Chan
发明人： Gregg R. Draudt , Dirk Ahlgrim , Jan Schminke , Mark Follman , José Colucci, JR. , Raymond Yao , Robert J. McCaffrey , Victor Chan
IPC分类号： A61B5/151
CPC分类号： A61B5/14532 , A61B5/150022 , A61B5/150175 , A61B5/150259 , A61B5/150358 , A61B5/15087 , A61B5/15113 , A61B5/15115 , A61B5/15186 , A61B5/1519 , A61B5/157 , A61B2562/0295 , G01N33/523 , G01N33/526 , G01N33/66
摘要： A blood glucose meter having a test strip port and an adjustable lancet device disposed at the same end of the device body is disclosed. The device body further includes an enclosure at the proximal end of the device body which houses a test strip storage vial and which facilitates one-handed opening and closing of the vial to simplify access to test strips contained therein. The enclosure is further provided with a window which allows the reading of the lot numbers on the label of the test strip vial therein without necessitating removal of the vial. A data connector is also provided on the device body for communication access, such as to upload data from other devices or to download data to other devices.
摘要翻译：公开了一种具有测试条端口和设置在装置本体的同一端的可调整的柳叶刀装置的血糖仪。装置主体还包括位于装置本体的近端处的壳体，其容纳测试条存储小瓶并且便于单手打开和关闭小瓶以简化对其中包含的测试条的访问。外壳还设置有窗口，其允许读取测试条瓶标签上的批号，而不需要移除小瓶。数据连接器还提供在设备主体上用于通信访问，例如从其他设备上传数据或将数据下载到其他设备。

9. 发明授权

US07505993B2 Database schema for content managed data 有权
标题翻译：内容管理数据的数据库模式
公开(公告)号：US07505993B2
公开(公告)日：2009-03-17
申请号：US11304015
申请日：2005-12-14
申请人： Victor Chan , Darl Andrew Crick , Miu-To Brenda Lam , Wan Ngai Wayne Lee , Jacob Vandergoot , Tony Chung Keung Woo
发明人： Victor Chan , Darl Andrew Crick , Miu-To Brenda Lam , Wan Ngai Wayne Lee , Jacob Vandergoot , Tony Chung Keung Woo
IPC分类号： G06F7/00 , G06F17/00
CPC分类号： G06F17/30595 , Y10S707/99943 , Y10S707/99944
摘要： Embodiments of the present invention is directed to a data structure in conformance with a database schema for accessing and managing content managed data and to a system, a method and a computer program product for creating the database schema. According to one embodiment of the invention, a method for creating a database schema for accessing and managing content managed data comprising the steps of: creating a base schema; creating a write schema; and creating a read schema; the database schema used by a business logic application to access and manipulate the content managed data in the database. Embodiment of the present invention manages changes to the data using the write schema and the read schema rather than by using a modified base schema.
摘要翻译：本发明的实施例涉及一种符合用于访问和管理内容管理数据的数据库模式的数据结构以及用于创建数据库模式的系统，方法和计算机程序产品。根据本发明的一个实施例，一种用于创建用于访问和管理内容管理数据的数据库模式的方法，包括以下步骤：创建基本模式; 创建一个写入模式; 并创建一个读模式; 业务逻辑应用程序使用的数据库模式来访问和操纵数据库中的内容管理数据。本发明的实施例使用写模式和读模式管理对数据的改变，而不是使用经修改的基本模式。

10. 发明申请

US20080290379A1 DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS 有权
标题翻译： CMOS混合方向的双路隔离
公开(公告)号：US20080290379A1
公开(公告)日：2008-11-27
申请号：US12169991
申请日：2008-07-09
申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
发明人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
IPC分类号： H01L21/8234 , H01L29/04
CPC分类号： H01L21/76229
摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
摘要翻译：本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第第一深度用于隔离相同极性的设备。本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

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