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    • 4. 发明授权
    • Dual trench isolation for CMOS with hybrid orientations
    • 具有混合取向的CMOS的双沟槽隔离
    • US08097516B2
    • 2012-01-17
    • US12169991
    • 2008-07-09
    • Victor ChanMeikei IeongRajesh RengarajanAlexander ReznicekChun-yung SungMin Yang
    • Victor ChanMeikei IeongRajesh RengarajanAlexander ReznicekChun-yung SungMin Yang
    • H01L21/336
    • H01L21/76229
    • The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
    • 本发明提供了一种半导体结构,其中不同类型的器件位于混合衬底的特定晶体取向上,这增强了每种器件的性能。 在本发明的半导体结构中,采用双沟槽隔离方案,由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离,而第二深度的第二沟槽隔离区比第 第一深度用于隔离相同极性的设备。 本发明还提供一种双沟槽半导体结构,其中pFET位于(110)结晶平面上,而nFET位于(100)晶面上。 根据本发明,不同极性的器件,即nFET和pFETs是大块状器件。
    • 7. 发明申请
    • DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
    • CMOS混合方向的双路隔离
    • US20120104511A1
    • 2012-05-03
    • US13349203
    • 2012-01-12
    • Victor ChanMeikei IeongRajesh RengarajanAlexander ReznicekChun-yung SungMin Yang
    • Victor ChanMeikei IeongRajesh RengarajanAlexander ReznicekChun-yung SungMin Yang
    • H01L27/092
    • H01L21/76229
    • The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
    • 本发明提供了一种半导体结构,其中不同类型的器件位于混合衬底的特定晶体取向上,这增强了每种器件的性能。 在本发明的半导体结构中,采用双沟槽隔离方案,由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离,而第二深度的第二沟槽隔离区比第 第一深度用于隔离相同极性的设备。 本发明还提供一种双沟槽半导体结构,其中pFET位于(110)结晶平面上,而nFET位于(100)晶面上。 根据本发明,不同极性的器件,即nFET和pFETs是大块状器件。
    • 10. 发明授权
    • Dual trench isolation for CMOS with hybrid orientations
    • 具有混合取向的CMOS的双沟槽隔离
    • US09355887B2
    • 2016-05-31
    • US13349203
    • 2012-01-12
    • Victor ChanMeikei IeongRajesh RengarajanAlexander ReznicekChun-yung SungMin Yang
    • Victor ChanMeikei IeongRajesh RengarajanAlexander ReznicekChun-yung SungMin Yang
    • H01L21/70H01L21/762
    • H01L21/76229
    • The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
    • 本发明提供了一种半导体结构,其中不同类型的器件位于混合衬底的特定晶体取向上,这增强了每种器件的性能。 在本发明的半导体结构中,采用双沟槽隔离方案,由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离,而第二深度的第二沟槽隔离区比第 第一深度用于隔离相同极性的设备。 本发明还提供一种双沟槽半导体结构,其中pFET位于(110)结晶平面上,而nFET位于(100)晶面上。 根据本发明,不同极性的器件,即nFET和pFETs是大块状器件。