会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 5. 发明申请
    • Multi-stable molecular device
    • 多稳态分子装置
    • US20070090344A1
    • 2007-04-26
    • US11256856
    • 2005-10-24
    • R. WilliamsPhilip KuekesAlexandre Bratkovski
    • R. WilliamsPhilip KuekesAlexandre Bratkovski
    • H01L29/08
    • H01L29/0665B82Y10/00B82Y30/00H01L29/0673
    • In accordance with the present invention, a molecular device is provided that can act as a finite state machine, such as a logic device or a memory device. The molecular device includes operating molecules having two or more rotors. Each rotor has an electric dipole moment and multiple discrete rotor configurational states. A rotor can be any suitable and effective group that has an electric dipole moment and multiple discrete rotor configurational states. An individual rotor configurational state can be substantially or completely independent of the rotor configurational states of other rotors. The rotor configurational states can be binary. The molecular configurational state of a multi-stable molecule of a device can be ascertained by measuring conductance.
    • 根据本发明,提供了可以用作有限状态机的分子装置,例如逻辑装置或存储装置。 分子装置包括具有两个或更多个转子的操作分子。 每个转子具有电偶极矩和多个离散的转子配置状态。 转子可以是具有电偶极矩和多个离散转子配置状态的任何合适且有效的组。 各个转子结构状态可以基本上或完全独立于其它转子的转子构型状态。 转子配置状态可以是二进制的。 可以通过测量电导来确定器件的多稳态分子的分子结构状态。
    • 6. 发明申请
    • Apparatus for imprinting lithography and fabrication thereof
    • 用于压印光刻及其制造的装置
    • US20070066070A1
    • 2007-03-22
    • US11601084
    • 2006-11-16
    • M. IslamGun JungYong ChenR. Williams
    • M. IslamGun JungYong ChenR. Williams
    • H01L21/465
    • H01L21/76838H01L21/0337
    • An imprinting apparatus and method of fabrication provide a mold having a pattern for imprinting. The apparatus includes a semiconductor substrate polished in a [110] direction. The semiconductor substrate has a (110) horizontal planar surface and vertical sidewalls of a wet chemical etched trench. The sidewalls are aligned with and therefore are (111) vertical lattice planes of the semiconductor substrate. The semiconductor substrate includes a plurality of vertical structures between the sidewalls, wherein the vertical structures may be nano-scale spaced apart. The method includes wet etching a trench with spaced apart (111) vertical sidewalls in an exposed portion of the (110) horizontal surface of the semiconductor substrate along (111) vertical lattice planes. A chemical etching solution is used that etches the (111) vertical lattice planes slower than the (110) horizontal lattice plane. The method further includes forming the imprinting mold.
    • 压印装置和制造方法提供具有用于压印的图案的模具。 该装置包括沿[110]方向抛光的半导体衬底。 半导体衬底具有(110)水平平面和湿化学蚀刻沟槽的垂直侧壁。 侧壁与半导体衬底对准并且因此是(111)垂直的晶格面。 半导体衬底包括在侧壁之间的多个垂直结构,其中垂直结构可以是纳米级隔开的。 该方法包括在(111)垂直晶格面的半导体衬底的(110)水平表面的暴露部分中湿式蚀刻具有间隔开(111)垂直侧壁的沟槽。 使用蚀刻比(110)水平晶格面慢的(111)垂直晶格面的化学蚀刻溶液。 该方法还包括形成压印模具。
    • 9. 发明申请
    • Nanowire device with (111) vertical sidewalls and method of fabrication
    • 具有(111)垂直侧壁的纳米线器件和制造方法
    • US20060006463A1
    • 2006-01-12
    • US10888628
    • 2004-07-09
    • M. IslamYong ChenShih-Yuan WangR. Williams
    • M. IslamYong ChenShih-Yuan WangR. Williams
    • H01L27/01H01L21/00
    • H01L27/1203B82Y10/00G11C2213/81H01L29/045H01L29/0665H01L29/0673H01L29/861
    • A nano-scale device and method of fabrication provide a nanowire having (111) vertical sidewalls. The nano-scale device includes a semiconductor-on-insulator substrate polished in a [110] direction, the nanowire, and an electrical contact at opposite ends of the nanowire. The method includes wet etching a semiconductor layer of the semiconductor-on-insulator substrate to form the nanowire extending between a pair of islands in the semiconductor layer. The method further includes depositing an electrically conductive material on the pair of islands to form the electrical contacts. A nano-pn diode includes the nanowire as a first nano-electrode, a pn-junction vertically stacked on the nanowire, and a second nano-electrode on a (110) horizontal planar end of the pn-junction. The nano-pn diode may be fabricated in an array of the diodes on the semiconductor-on-insulator substrate.
    • 纳米级器件和制造方法提供具有(111)垂直侧壁的纳米线。 纳米级器件包括在[110]方向上抛光的绝缘体上半导体衬底,纳米线和在纳米线的相对端的电接触。 该方法包括湿式蚀刻绝缘体上半导体衬底的半导体层,以形成在半导体层中的一对岛之间延伸的纳米线。 该方法还包括在一对岛上沉积导电材料以形成电触头。 纳米pn二极管包括纳米线作为第一纳米电极,垂直堆叠在纳米线上的pn结,以及在pn结的(110)水平平面端上的第二纳米电极。 可以在绝缘体上半导体衬底上的二极管的阵列中制造纳米pn二极管。