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1. 发明授权

US08449232B2 Indexing device for machine tool 有权
标题翻译：机床分度装置
公开(公告)号：US08449232B2
公开(公告)日：2013-05-28
申请号：US12522217
申请日：2007-11-12
申请人： Yoshinori Tatsuda , Youichi Nishida
发明人： Yoshinori Tatsuda , Youichi Nishida
IPC分类号： B23B31/30
CPC分类号： B23B31/30 , B23Q1/287 , B23Q1/5406 , B23Q16/102 , B23Q2220/006 , Y10T279/12 , Y10T279/1216 , Y10T279/13 , Y10T279/21 , Y10T409/307672
摘要： A cylindrical pressure-receiving member 34b is arranged in a space between a ring-shaped clamp sleeve 34a and a frame 31b such that the clamp sleeve 34a is fitted around a shaft 38b being integral with a rotary shaft 39. In an outer peripheral portion 34a2 of the clamp sleeve 34a, an annular groove 34a1 provided continuously over the entire circumference within an axial area of the outer peripheral portion 34a2 fitted into an inner peripheral portion 34b3 of the pressure-receiving member 34b provides a thin-wall portion 34a5. Also, a space surrounded by the annular groove 34a5 and the pressure-receiving member 34b provides a pressure chamber 34d communicating with a fluid control circuit. A predetermined gap 34d2 is provided between an inner peripheral surface 31b4 of the through hole 31b1 of the frame and an outer peripheral surface 34b2 of the pressure-receiving member 34b.
摘要翻译：在环形夹紧套筒34a和框架31b之间的空间内设置圆柱形的受压部件34b，使得夹紧套筒34a围绕与旋转轴39成一体的轴38b嵌合。在外周部分34a2 夹紧套筒34a的内周部34b3的外周部34a2的轴向区域内连续设置的环状槽34a1形成有薄壁部34a5。此外，由环形槽34a5和受压构件34b包围的空间提供与流体控制电路连通的压力室34d。在框架的通孔31b1的内周表面31b4和受压构件34b的外周表面34b2之间设置预定间隙34d2。

2. 发明申请

US20100084828A1 INDEXING DEVICE FOR MACHINE TOOL 有权
标题翻译：机床工具指导装置
公开(公告)号：US20100084828A1
公开(公告)日：2010-04-08
申请号：US12522217
申请日：2007-11-12
申请人： Yoshinori Tatsuda , Youichi Nishida
发明人： Yoshinori Tatsuda , Youichi Nishida
IPC分类号： B23Q16/10 , B23Q1/28
CPC分类号： B23B31/30 , B23Q1/287 , B23Q1/5406 , B23Q16/102 , B23Q2220/006 , Y10T279/12 , Y10T279/1216 , Y10T279/13 , Y10T279/21 , Y10T409/307672
摘要： A cylindrical pressure-receiving member 34b is arranged in a space between a ring-shaped clamp sleeve 34a and a frame 31b such that the clamp sleeve 34a is fitted around a shaft 38b being integral with a rotary shaft 39. In an outer peripheral portion 34a2 of the clamp sleeve 34a, an annular groove 34a1 provided continuously over the entire circumference within an axial area of the outer peripheral portion 34a2 fitted into an inner peripheral portion 34b3 of the pressure-receiving member 34b provides a thin-wall portion 34a5. Also, a space surrounded by the annular groove 34a5 and the pressure-receiving member 34b provides a pressure chamber 34d communicating with a fluid control circuit. A predetermined gap 34d2 is provided between an inner peripheral surface 31b4 of the through hole 31b1 of the frame and an outer peripheral surface 34b2 of the pressure-receiving member 34b.
摘要翻译：在环形夹紧套筒34a和框架31b之间的空间内设置圆柱形的受压部件34b，使得夹紧套筒34a围绕与旋转轴39成一体的轴38b嵌合。在外周部分34a2 夹紧套筒34a的内周部34b3的外周部34a2的轴向区域内连续设置的环状槽34a1形成有薄壁部34a5。此外，由环形槽34a5和受压构件34b包围的空间提供与流体控制电路连通的压力室34d。在框架的通孔31b1的内周表面31b4和受压构件34b的外周表面34b2之间设置预定间隙34d2。

3. 发明申请

US20100019427A1 CLAMPING DEVICE OF INDEXING DEVICE FOR MACHINE TOOL 审中-公开
标题翻译：用于机床的指针装置的夹紧装置
公开(公告)号：US20100019427A1
公开(公告)日：2010-01-28
申请号：US12574056
申请日：2009-10-06
申请人： Youichi Nishida
发明人： Youichi Nishida
IPC分类号： B23Q16/02 , B23Q16/04 , B23Q1/25
CPC分类号： B23Q16/105 , B23Q16/06 , B23Q16/102 , B23Q2220/004
摘要： A clamping device for holding an indexed angular position of a main shaft includes a clamp section non-rotatable relative to the main shaft, and a pressing mechanism including a clamp piston displaceable in an axial direction of the main shaft and causing a fluid pressure received by the clamp piston to act on the clamp section. The clamp section includes a first clamp portion being non-rotatable relative to the main shaft, and a second clamp portion being rotatable with the main shaft. The pressing mechanism includes first and second pressing portions which respectively press the first and second clamp portions. The second clamp portion or the second pressing portion is elastically displaced when the clamp piston advances by the fluid pressure. Forces in axial and radial directions are respectively applied to the first and second clamp portions, thereby clamping the main shaft.
摘要翻译：用于保持主轴的分度角位置的夹紧装置包括相对于主轴不能旋转的夹紧部分，以及包括可沿主轴的轴向方向移位的夹紧活塞的压紧机构，夹紧活塞作用在夹紧部分上。夹持部分包括相对于主轴不可旋转的第一夹持部分和可与主轴一起旋转的第二夹紧部分。按压机构包括分别按压第一和第二夹持部的第一和第二按压部。当夹紧活塞前进流体压力时，第二夹紧部分或第二按压部分弹性位移。轴向和径向的力分别施加到第一和第二夹紧部分，从而夹紧主轴。

4. 发明授权

US06469937B2 Current sense amplifier circuit 有权
公开(公告)号：US06469937B2
公开(公告)日：2002-10-22
申请号：US10040788
申请日：2002-01-09
申请人： Ikuo Fuchigami , Tomonori Kataoka , Youichi Nishida , Tomoo Kimura , Jyunji Michiyama , Satoshi Kohtaka
发明人： Ikuo Fuchigami , Tomonori Kataoka , Youichi Nishida , Tomoo Kimura , Jyunji Michiyama , Satoshi Kohtaka
IPC分类号： G11C1606
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062 , G11C7/067 , G11C11/56 , G11C11/5621 , G11C16/28 , G11C2207/063 , G11C2211/5634
摘要： A current sense amplifier circuit is provided with a reference current generator for generating a reference current according to the characteristics of a memory cell, and a current comparator, and the current comparator compares the memory cell current with the reference current. Thereby, the range of the operating power supply voltage is increased. Further, a current sense amplifier circuit is provided with plural sets of reference current generators and current comparators, and the reference current generators generate reference currents of different amounts corresponding to plural states the memory cell can take, and the current comparators compare the respective reference currents with the memory cell current. Therefore, it is possible to detect the current in the memory cell that is set in multiple states.

5. 发明授权

US06351416B2 Current sense amplifier circuit 失效
公开(公告)号：US06351416B2
公开(公告)日：2002-02-26
申请号：US09796806
申请日：2001-03-02
申请人： Ikuo Fuchigami , Tomonori Kataoka , Youichi Nishida , Tomoo Kimura , Jyunji Michiyama , Satoshi Kohtaka
发明人： Ikuo Fuchigami , Tomonori Kataoka , Youichi Nishida , Tomoo Kimura , Jyunji Michiyama , Satoshi Kohtaka
IPC分类号： G11C1606
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062 , G11C7/067 , G11C11/56 , G11C11/5621 , G11C16/28 , G11C2207/063 , G11C2211/5634
摘要： A current sense amplifier circuit is provided with a reference current generator for generating a reference current according to the characteristics of a memory cell, and a current comparator, and the current comparator compares the memory cell current with the reference current. Thereby, the range of the operating power supply voltage is increased. Further, a current sense amplifier circuit is provided with plural sets of reference current generators and current comparators, and the reference current generators generate reference currents of different amounts corresponding to plural states the memory cell can take, and the current comparators compare the respective reference currents with the memory cell current. Therefore, it is possible to detect the current in the memory cell that is set in multiple states.

6. 发明授权

US06208124B1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06208124B1
公开(公告)日：2001-03-27
申请号：US09586993
申请日：2000-06-05
申请人： Ikuo Fuchigami , Tomonori Kataoka , Youichi Nishida , Tomoo Kimura
发明人： Ikuo Fuchigami , Tomonori Kataoka , Youichi Nishida , Tomoo Kimura
IPC分类号： G05F140
CPC分类号： G05F1/565 , Y10T307/25
摘要： A semiconductor integrated circuit includes a booster for boosting a power supply voltage, and outputting the boosted voltage; an output circuit being supplied with the boosted voltage, and generating an output voltage from the boosted voltage; a reference voltage generator being supplied with the power supply voltage, and generating a reference voltage from the power supply voltage; a voltage divider being supplied with the output voltage from the output circuit, and dividing the output voltage with a predetermined voltage ratio; and a differential amplifier being supplied with the reference voltage and the divided voltage, and controlling the output circuit by supplying the output circuit with a voltage obtained by performing differential amplification on the reference voltage and the divided voltage according to the power supply voltage, thereby maintaining the output voltage from the output circuit at a predetermined voltage. In this circuit, since the reference voltage generator and the differential amplifier are operated with the power supply voltage, it is not necessary to supply the boosted voltage to them, whereby the output current from the booster is reduced. Therefore, undesired reduction in the boosted voltage due to an increase in the output current is suppressed. As the result, the capacitance used in the booster is reduced, and the area of the semiconductor integrated circuit is reduced.
摘要翻译：半导体集成电路包括用于升压电源电压并输出升压电压的升压器; 输出电路被提供升压电压，并从升压电压产生输出电压; 参考电压发生器被提供有电源电压，并从电源电压产生参考电压; 分压器从输出电路提供输出电压，并以预定的电压比划分输出电压; 并且差分放大器被提供有参考电压和分压，并且通过向输出电路提供根据电源电压对参考电压和分压进行差分放大而获得的电压来控制输出电路，从而保持在预定电压下来自输出电路的输出电压。在该电路中，由于参考电压发生器和差分放大器以电源电压工作，所以不需要向其提供升压电压，从而降低了来自升压器的输出电流。因此，抑制了由于输出电流的增加引起的升压电压的不希望的降低。结果，减小了增强器中使用的电容，并且减小了半导体集成电路的面积。

7. 发明授权

US07089431B2 Data processing system for reducing wasteful power consumption 有权
标题翻译：用于减少浪费电力消耗的数据处理系统
公开(公告)号：US07089431B2
公开(公告)日：2006-08-08
申请号：US10352850
申请日：2003-01-29
申请人： Masatoshi Matsuo , Youichi Nishida , Takashi Hashimoto , Masahiro Ohashi , Hiroto Tomita
发明人： Masatoshi Matsuo , Youichi Nishida , Takashi Hashimoto , Masahiro Ohashi , Hiroto Tomita
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , Y02D10/128 , Y02D10/159 , Y02D10/171
摘要： An image processing unit decodes coded data that have been coded and synthesizes the decoded moving image with graphics data. In a case where only graphics data are to be displayed, a bypass unit outputs the graphics data to a display device without use of an image processing unit. A control unit performs control of the supplying of a power supply voltage and a clock to a region containing the image processing unit and performs control of the bypass unit. If processing at the image processing unit is unnecessary, the supply of a power supply voltage or the supply of a clock to the region containing the image processing unit is stopped so as to stop the region and enable reduction of wasteful power consumption.
摘要翻译：图像处理单元对已编码的编码数据进行解码，并用图形数据合成解码的运动图像。在仅显示图形数据的情况下，旁路单元将图形数据输出到显示装置，而不使用图像处理单元。控制单元执行向包含图像处理单元的区域提供电源电压和时钟的控制，并执行旁路单元的控制。如果不需要图像处理单元的处理，则停止向包含图像处理单元的区域提供电源电压或提供时钟，以便停止该区域并且能够减少浪费的功率消耗。

8. 发明申请

US20070192565A1 Semiconductor device and mobile phone using the same 审中-公开
标题翻译：半导体器件和手机使用相同
公开(公告)号：US20070192565A1
公开(公告)日：2007-08-16
申请号：US10575784
申请日：2005-03-28
申请人： Masashi Hoshino , Masayoshi Tojima , Youichi Nishida
发明人： Masashi Hoshino , Masayoshi Tojima , Youichi Nishida
IPC分类号： G06F15/00
CPC分类号： G06F15/7832
摘要： A semiconductor device (100) comprises a processor unit (110) including an internal CPU (113), an internal interface section (130), an external interface section (140) including an interface unit (143) connected to an external CPU (201), a plurality of processing circuits (121)-(126), and a connection control circuit (180). The internal interface section (130) includes a first bus (191) connected to the internal CPU (113), a second bus (192) connected to the external CPU (201) through the interface unit (143), and selecting circuits (131)-(136), controlled by the connection control circuit (180) according to the instruction of the internal CPU (113) or the external CPU (201), and operable to select respective connections of the plurality of processing circuits (121)-(126) to the first bus (191) or to the second bus (192). All the processing circuits (121)-(126) are controllable by the internal CPU (113) and the external CPU (201).
摘要翻译：一种半导体器件（100），包括：处理器单元（110），包括内部CPU（113），内部接口部分（130），外部接口部分（140），其包括连接到外部CPU（201）的接口单元），多个处理电路（121） - （126）和连接控制电路（180）。内部接口部分（130）包括连接到内部CPU（113）的第一总线（191），通过接口单元（143）连接到外部CPU（201）的第二总线（192），以及选择电路） - （136），由连接控制电路（180）根据内部CPU（113）或外部CPU（201）的指令控制，并且可操作以选择多个处理电路（121）的各个连接 - （126）连接到第一总线（191）或第二总线（192）。所有处理电路（121） - （126）都可由内部CPU（113）和外部CPU（201）控制。

9. 发明授权

US06219286B1 Semiconductor memory having reduced time for writing defective information 有权
标题翻译：半导体存储器具有减少写入缺陷信息的时间
公开(公告)号：US06219286B1
公开(公告)日：2001-04-17
申请号：US09586992
申请日：2000-06-05
申请人： Ikuo Fuchigami , Tomonori Kataoka , Youichi Nishida , Tomoo Kimura , Ken Kawai
发明人： Ikuo Fuchigami , Tomonori Kataoka , Youichi Nishida , Tomoo Kimura , Ken Kawai
IPC分类号： G11C700
CPC分类号： G11C29/848
摘要： The present invention provides a semiconductor memory which can reduce the area of a circuit for replacing defective memory cells with redundant memory cells as well as reduce the time for writing defect information. The semiconductor memory of the present invention comprises a memory cell array 1 comprising (n+1) (n is a positive integer) word lines, a register unit 4 holding an encoded defect address for specifying a defective word line, a defect address decoder 31 for decoding the defect address from the register unit 4 to specify the defective word line, selection means S1˜Sn for selecting, for the i-th (1≦i≦n) output signal line of a row decoder 2, one of the i-th and i+1-th word lines and connecting the selected word line to the i-th output signal line, and control means C1˜Cn each controlling corresponding one of the selection means S1˜Sn on the basis of an output of the defect address decoder 31 so as to select, for the output signal line of the row decoder 2, one of the word lines except the defective word line in accordance with the arrangement order.
摘要翻译：本发明提供一种半导体存储器，其可以减少用于用冗余存储器单元替换有缺陷的存储单元的电路的面积，并且减少写入缺陷信息的时间。本发明的半导体存储器包括存储单元阵列1，其包括（n + 1）（n是正整数）字线，保持用于指定缺陷字线的编码缺陷地址的寄存器单元4，缺陷地址解码器31 为了从寄存器单元4解码缺陷地址以指定缺陷字线，对于行解码器2的第i（1 <= i <= n）个输出信号线，选择装置S1〜Sn选择第i个和第i个第1个字线并将选择的字线连接到第i个输出信号线，以及控制装置C1〜Cn，每个控制装置C1〜Cn根据输出对于行解码器2的输出信号线，根据排列顺序选择除缺陷字线以外的字线之一。

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