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    • 2. 发明授权
    • Icing detector probe and icing detector with the same
    • 结冰检测器探头和结冰探测器相同
    • US09079669B2
    • 2015-07-14
    • US13809934
    • 2011-06-30
    • Yingchun ChenLin YeMiao ZhangJunfeng GeLijuan FengTiejun LiuFeng Zhou
    • Yingchun ChenLin YeMiao ZhangJunfeng GeLijuan FengTiejun LiuFeng Zhou
    • B64D15/20
    • B64D15/20
    • An icing detector probe includes three sections arranged sequentially along the direction of air flow, namely, a first section, a second section and a third section. The shape of the outer surface of the first section is suitable for collecting droplets in the air flow. The shape of the outer surface of the second section is suitable for full decelerating and releasing latent heat of large droplets during their movements. The outer surface of the third section is suitable for icing of large droplets. The probe detects icing by distinguishing and identify large droplets icing. The probe effectively detects types of traditional icing, thus being helpful for exact detection of icing thickness. An icing detector including said icing detector probe is also provided.
    • 结冰检测器探头包括沿空气流动方向依次布置的三个部分,即第一部分,第二部分和第三部分。 第一部分的外表面的形状适合于在空气流中收集液滴。 第二部分的外表面的形状适合于在其运动期间完全减速和释放大液滴的潜热。 第三部分的外表面适用于大液滴的结冰。 探测器通过识别和识别大型液滴结冰来检测结冰。 探头有效地检测传统结冰的类型,有助于精确检测结冰厚度。 还提供了包括所述结冰检测器探针的结冰检测器。
    • 4. 发明申请
    • Method for Preparing GOI Chip Structure
    • 制备GOI芯片结构的方法
    • US20140004684A1
    • 2014-01-02
    • US13825010
    • 2012-09-25
    • Zengfeng DiLin YeZhongying XueMiao Zhang
    • Zengfeng DiLin YeZhongying XueMiao Zhang
    • H01L21/762
    • H01L21/76254
    • The present invention provides a method for preparing a GOI chip structure, where, in the method, first, a SiGe on insulator (SGOI) chip structure is made by using a Smart-Cut technology, and then, germanium condensation technology is performed on the SGOI chip structure, so as to obtain a GOI chip structure. Because the SGOI made by the Smart-Cut technology basically has no misfit dislocation in an SGOI/BOX interface, the threading dislocation density of the GOI is finally reduced. A technique of the present invention is simple, the high-quality GOI chip structure can be implemented, and the germanium condensation technology is greatly improved. An ion implantation technology and an annealing technology are quite mature techniques in the current semiconductor industry, so that such a preparation method greatly improves the possibility of wide use of the germanium concentration technology in the semiconductor industry.
    • 本发明提供了一种制备GOI芯片结构的方法,其中在该方法中,首先通过使用Smart-Cut技术制造绝缘体上的SiGe(SGOI)芯片结构,然后在 SGOI芯片结构,从而获得GOI芯片结构。 由于采用智能切割技术制成的SGOI基本上在SGOI / BOX接口中没有错配位错,因此GOI的穿透位错密度最终降低。 本发明的技术简单,可以实现高质量的GOI芯片结构,并且锗冷凝技术得到极大改善。 离子注入技术和退火技术在目前的半导体工业中是相当成熟的技术,因此这种制备方法大大提高了半导体工业中锗浓缩技术的广泛应用的可能性。
    • 5. 发明授权
    • Method for preparing GOI chip structure
    • 制备GOI芯片结构的方法
    • US08877608B2
    • 2014-11-04
    • US13825010
    • 2012-09-25
    • Zengfeng DiLin YeZhongying XueMiao Zhang
    • Zengfeng DiLin YeZhongying XueMiao Zhang
    • H01L21/46H01L21/762
    • H01L21/76254
    • The present invention provides a method for preparing a GOI chip structure, where, in the method, first, a SiGe on insulator (SGOI) chip structure is made by using a SMART CUT technology, and then, germanium condensation technology is performed on the SGOI chip structure, so as to obtain a GOI chip structure. Because the SGOI made by the Smart-Cut technology basically has no misfit dislocation in an SGOI/BOX interface, the threading dislocation density of the GOI is finally reduced. A technique of the present invention is simple, the high-quality GOI chip structure can be implemented, and the germanium condensation technology is greatly improved. An ion implantation technology and an annealing technology are quite mature techniques in the current semiconductor industry, so that such a preparation method greatly improves the possibility of wide use of the germanium concentration technology in the semiconductor industry.
    • 本发明提供了一种制备GOI芯片结构的方法,其中在该方法中,首先通过使用SMART CUT技术制造绝缘体上硅锗(SGOI)芯片结构,然后在SGOI上进行锗冷凝技术 芯片结构,从而获得GOI芯片结构。 由于采用智能切割技术制成的SGOI基本上在SGOI / BOX接口中没有错配位错,因此GOI的穿透位错密度最终降低。 本发明的技术简单,可以实现高质量的GOI芯片结构,并且锗冷凝技术得到极大改善。 离子注入技术和退火技术在目前的半导体工业中是相当成熟的技术,因此这种制备方法大大提高了半导体工业中锗浓缩技术的广泛应用的可能性。
    • 9. 发明授权
    • Integrated post-etch treatment for a dielectric etch process
    • 用于电介质蚀刻工艺的集成后蚀刻处理
    • US06379574B1
    • 2002-04-30
    • US09320251
    • 1999-05-26
    • Hui Ou-YangChih-Ping YangLin YeRobert W. WuChih-Pang ChenYou-Neng ChengYang Chan-LonTong-Yu Chen
    • Hui Ou-YangChih-Ping YangLin YeRobert W. WuChih-Pang ChenYou-Neng ChengYang Chan-LonTong-Yu Chen
    • B44C122
    • H01L21/02063H01L21/31116
    • The present disclosure pertains to an integrated post-etch treatment method which is performed after a dielectric etch process. Using the method of the invention, byproducts formed on the sidewalls of contact vias during the dielectric etch process can be removed efficiently. The method of the invention also reduces or eliminates the problem of polymer accumulation on process chamber surfaces. An overlying photoresist layer and anti-reflection layer are removed during the performance of the post-etch treatment method. Typically, after the etch of a dielectric material to define pattern or interconnect filling spaces, a series of post-etch treatment steps is performed to remove residues remaining on the wafer after the dielectric etch process. According to the method of the present invention, a post-etch treatment method including one or more steps is performed after the dielectric etch process, preferably within the same processing chamber in which the dielectric etch process was performed. The post-etch treatment method comprises exposing a semiconductor structure to a plasma generated from a source gas comprising oxygen, a nitrogen-comprising gas, and a reactive gas comprising hydrogen, carbon, and fluorine. Two optional steps, a flushing step prior to the post-etch treatment and a cleaning step subsequent to the post-etch treatment, can be performed for the purpose of enhancing the fluorine and byproduct removal and post-etch chamber cleaning.
    • 本公开涉及在电介质蚀刻工艺之后执行的集成后蚀刻处理方法。 使用本发明的方法,可以有效地去除在电介质蚀刻工艺期间在接触通孔的侧壁上形成的副产物。 本发明的方法还减少或消除了聚合物在处理室表面上积聚的问题。 在蚀刻后处理方法的执行期间,去除覆盖的光致抗蚀剂层和抗反射层。 通常,在蚀刻电介质材料以限定图案或互连填充空间之后,执行一系列后蚀刻处理步骤以在电介质蚀刻工艺之后去除残留在晶片上的残留物。 根据本发明的方法,在电介质蚀刻工艺之后,优选在进行电介质蚀刻工艺的相同处理室内执行包括一个或多个步骤的后蚀刻处理方法。 蚀刻后处理方法包括将半导体结构暴露于由包含氧,含氮气体和包含氢,碳和氟的反应性气体的源气体产生的等离子体。 可以执行两个可选步骤,即在蚀刻后处理之前的冲洗步骤和在蚀刻后处理之后的清洁步骤,以便增强氟和副产物去除以及蚀刻后清洁。