专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09230849B2 Method for preparing ultra-thin material on insulator through adsorption by doped ultra-thin layer 有权
标题翻译：通过掺杂超薄层吸附制备绝缘体上的超薄材料的方法
公开(公告)号：US09230849B2
公开(公告)日：2016-01-05
申请号：US13825079
申请日：2012-09-25
申请人： Zengfeng Di , Da Chen , Jiantao Bian , Zhongying Xue , Miao Zhang
发明人： Zengfeng Di , Da Chen , Jiantao Bian , Zhongying Xue , Miao Zhang
IPC分类号： H01L21/30 , H01L21/762 , H01L21/306
CPC分类号： H01L21/76254 , H01L21/30604 , H01L21/30625
摘要： The present invention provides a method for preparing an ultra-thin material on insulator through adsorption by a doped ultra-thin layer. In the method, first, an ultra-thin doped single crystal film and an ultra-thin top film (or contains a buffer layer) are successively and epitaxially grown on a first substrate, and then a high-quality ultra-thin material on insulator is prepared through ion implantation and a bonding process. A thickness of the prepared ultra-thin material on insulator ranges from 5 nm to 50 nm. In the present invention, the ultra-thin doped single crystal film adsorbs the implanted ion, and a micro crack is then formed, so as to implement ion-cut; therefore, the roughness of a surface of a ion-cut material on insulator is small. In addition, an impurity atom strengthens an ion adsorption capability of the ultra-thin single crystal film, so that an ion implantation dose and the annealing temperature can be lowered in the preparation procedure, thereby effectively reducing the damage caused by the implantation to the top film, and achieving objectives of improving production efficiency and reducing the production cost.
摘要翻译：本发明提供一种通过掺杂超薄层吸附制备绝缘体上的超薄材料的方法。在该方法中，首先，在第一基板上依次外延生长超薄掺杂单晶膜和超薄顶膜（或包含缓冲层），然后在绝缘体上形成高品质超薄材料通过离子注入和粘合工艺制备。所制备的绝缘体上的超薄材料的厚度范围为5nm至50nm。在本发明中，超薄掺杂单晶膜吸附注入的离子，然后形成微裂纹，从而实现离子切割; 因此，绝缘体上的离子切割材料的表面的粗糙度小。此外，杂质原子增强了超薄单晶膜的离子吸附能力，使得在制备过程中可以降低离子注入剂量和退火温度，从而有效地减少了植入到顶部的损伤电影，实现提高生产效率和降低生产成本的目标。

2. 发明申请

US20140004684A1 Method for Preparing GOI Chip Structure 有权
标题翻译：制备GOI芯片结构的方法
公开(公告)号：US20140004684A1
公开(公告)日：2014-01-02
申请号：US13825010
申请日：2012-09-25
申请人： Zengfeng Di , Lin Ye , Zhongying Xue , Miao Zhang
发明人： Zengfeng Di , Lin Ye , Zhongying Xue , Miao Zhang
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： The present invention provides a method for preparing a GOI chip structure, where, in the method, first, a SiGe on insulator (SGOI) chip structure is made by using a Smart-Cut technology, and then, germanium condensation technology is performed on the SGOI chip structure, so as to obtain a GOI chip structure. Because the SGOI made by the Smart-Cut technology basically has no misfit dislocation in an SGOI/BOX interface, the threading dislocation density of the GOI is finally reduced. A technique of the present invention is simple, the high-quality GOI chip structure can be implemented, and the germanium condensation technology is greatly improved. An ion implantation technology and an annealing technology are quite mature techniques in the current semiconductor industry, so that such a preparation method greatly improves the possibility of wide use of the germanium concentration technology in the semiconductor industry.
摘要翻译：本发明提供了一种制备GOI芯片结构的方法，其中在该方法中，首先通过使用Smart-Cut技术制造绝缘体上的SiGe（SGOI）芯片结构，然后在 SGOI芯片结构，从而获得GOI芯片结构。由于采用智能切割技术制成的SGOI基本上在SGOI / BOX接口中没有错配位错，因此GOI的穿透位错密度最终降低。本发明的技术简单，可以实现高质量的GOI芯片结构，并且锗冷凝技术得到极大改善。离子注入技术和退火技术在目前的半导体工业中是相当成熟的技术，因此这种制备方法大大提高了半导体工业中锗浓缩技术的广泛应用的可能性。

3. 发明申请

US20130029478A1 METHOD OF FABRICATING HIGH-MOBILITY DUAL CHANNEL MATERIAL BASED ON SOI SUBSTRATE 失效
标题翻译：基于SOI衬底制造高活性双通道材料的方法
公开(公告)号：US20130029478A1
公开(公告)日：2013-01-31
申请号：US13262656
申请日：2011-07-25
申请人： Miao Zhang , Bo Zhang , Zhongying Xue , Xi Wang
发明人： Miao Zhang , Bo Zhang , Zhongying Xue , Xi Wang
IPC分类号： H01L21/20
CPC分类号： H01L21/76251 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： The present invention discloses a method of fabricating high-mobility dual channel material based on SOI substrate, wherein compressive strained SiGe is epitaxially grown on a conventional SOI substrate to be used as channel material of PMOSFET; Si is then epitaixally grown on SiGe, and approaches such as ion implantation and annealing are employed to allow relaxation of part of strained SiGe and transfer strain to the Si layer thereon so as to form strained Si material as channel material of NMOSFET. With simple process and easy realization, this method can provide high-mobility channel material for NMOSFET and PMOSFET at the same time, well meeting the requirement of simultaneously enhancing the performance of NMOSFET and PMOSFET devices and therefore providing potential channel material for CMOS process of the next generation.
摘要翻译：本发明公开了一种制造基于SOI衬底的高迁移率双通道材料的方法，其中压缩应变SiGe在常规SOI衬底上外延生长以用作PMOSFET的沟道材料; Si在SiGe上表面生长，采用离子注入和退火等方法，使部分应变SiGe弛豫并向其上的Si层转移应变，形成作为NMOSFET的沟道材料的应变Si材料。通过简单的工艺和易于实现，该方法可以同时为NMOSFET和PMOSFET提供高迁移率沟道材料，可以很好地满足NMOSFET和PMOSFET器件同时提高性能的要求，从而为CMOS工艺提供潜在的沟道材料下一代。

4. 发明授权

US08274119B2 Hybrid material accumulation mode GAA CMOSFET 失效
标题翻译：混合材料堆积模式GAA CMOSFET
公开(公告)号：US08274119B2
公开(公告)日：2012-09-25
申请号：US12810648
申请日：2010-02-11
申请人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
发明人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
IPC分类号： H01L21/70
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L27/1211 , H01L29/42392 , H01L29/78696
摘要： A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device has high carrier mobility, high device drive current, and maintains the electrical integrity of the device. Meanwhile, polysilicon gate depletion and short channel effects are prevented.
摘要翻译： Ge和Si混合材料堆积模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。第一通道和第二通道具有跑道形横截面并分别由p型Ge和n型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。在积累模式中，电流流过整个跑道状通道。所公开的器件具有高的载流子迁移率，高的器件驱动电流，并且保持器件的电气完整性。同时，防止了多晶硅栅极耗尽和短沟道效应。

5. 发明授权

US08274118B2 Hybrid material accumulation mode GAA CMOSFET 失效
标题翻译：混合材料堆积模式GAA CMOSFET
公开(公告)号：US08274118B2
公开(公告)日：2012-09-25
申请号：US12810594
申请日：2010-02-11
申请人： DEYuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
发明人： DEYuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
IPC分类号： H01L21/70
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823821 , H01L27/12 , H01L29/42392 , H01L29/78696
摘要： A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device.
摘要翻译： Ge和Si混合材料堆积模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。第一通道和第二通道具有圆形截面并分别由p型Ge和n型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。在累积模式下，电流流过整个圆柱形通道，以实现高载流子迁移率，降低低频噪声，防止多晶硅栅极耗尽和短沟道效应，并增加器件的阈值电压。

6. 发明申请

US20110254102A1 HYBRID ORIENTATION INVERSION MODE GAA CMOSFET 失效
标题翻译：混合方向反相模式GAA CMOSFET
公开(公告)号：US20110254102A1
公开(公告)日：2011-10-20
申请号：US12810740
申请日：2010-02-11
申请人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
发明人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
IPC分类号： H01L27/092
CPC分类号： H01L27/1211 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1203 , H01L29/42392 , H01L29/78696
摘要： A hybrid orientation inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Si (110) and p-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an inversion mode, the devices have different orientation channels, the GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, and prevent polysilicon gate depletion and short channel effects.
摘要翻译：混合取向反转模式GAA（Gate-All-Around）CMOSFET包括具有第一通道的PMOS区域，具有第二通道的NMOS区域和栅极区域。第一通道和第二通道具有跑道形横截面并分别由n型Si（110）和p型Si（100）形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。根据本发明的装置结构相当简单，紧凑且高度集成。在反转模式中，器件具有不同的取向通道，GAA结构具有跑道形，高k栅介质层和金属栅极，从而实现高载流子迁移率，并防止多晶硅栅极耗尽和短沟道效应。

7. 发明申请

US20110254099A1 Hybrid material accumulation mode GAA CMOSFET 失效
标题翻译：混合材料堆积模式GAA CMOSFET
公开(公告)号：US20110254099A1
公开(公告)日：2011-10-20
申请号：US12810594
申请日：2010-02-11
申请人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
发明人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
IPC分类号： H01L27/092
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823821 , H01L27/12 , H01L29/42392 , H01L29/78696
摘要： A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device.
摘要翻译： Ge和Si混合材料堆积模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。第一通道和第二通道具有圆形截面并分别由p型Ge和n型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。在累积模式下，电流流过整个圆柱形通道，以实现高载流子迁移率，降低低频噪声，防止多晶硅栅极耗尽和短沟道效应，并增加器件的阈值电压。

8. 发明授权

US08330229B2 Hybrid orientation inversion mode GAA CMOSFET 失效
标题翻译：混合方向反演模式GAA CMOSFET
公开(公告)号：US08330229B2
公开(公告)日：2012-12-11
申请号：US12810740
申请日：2010-02-11
申请人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
发明人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
IPC分类号： H01L27/092
CPC分类号： H01L27/1211 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1203 , H01L29/42392 , H01L29/78696
摘要： A hybrid orientation inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Si (110) and p-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an inversion mode, the devices have different orientation channels, the GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, and prevent polysilicon gate depletion and short channel effects.
摘要翻译：混合取向反转模式GAA（Gate-All-Around）CMOSFET包括具有第一通道的PMOS区域，具有第二通道的NMOS区域和栅极区域。第一通道和第二通道具有跑道形横截面并分别由n型Si（110）和p型Si（100）形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。根据本发明的装置结构相当简单，紧凑且高度集成。在反转模式中，器件具有不同的取向通道，GAA结构具有跑道形，高k栅介质层和金属栅极，从而实现高载流子迁移率，并防止多晶硅栅极耗尽和短沟道效应。

9. 发明申请

US20110221002A1 MOS-TYPE ESD PROTECTION DEVICE IN SOI AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译： SOI中的MOS型ESD保护器件及其制造方法
公开(公告)号：US20110221002A1
公开(公告)日：2011-09-15
申请号：US13055553
申请日：2010-07-14
申请人： Jing Chen , Jiexin Luo , Qingqing Wu , Bingxu Ning , Zhongying Xue , Xiaolu Huang , Xi Wang
发明人： Jing Chen , Jiexin Luo , Qingqing Wu , Bingxu Ning , Zhongying Xue , Xiaolu Huang , Xi Wang
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/0266
摘要： The present invention discloses a MOS ESD protection device for SOI technology and a manufacturing method for the device. The MOS ESD protection device comprises: an epitaxial silicon layer grown on top of an SOI substrate; a first side-wall spacer disposed on both sides of the epitaxial silicon layer so as to isolate the ESD protection device from the intrinsic active structures; a source region and a drain region disposed respectively on two sides of the epitaxial silicon layer; a poly silicon gate and a gate dielectric formed on top of the epitaxial silicon layer; and a second side-wall spacer disposed on both sides of the poly silicon gate of . ESD leakage current passes down to the SOI substrate for protection. Because ESD protection device and intrinsic MOS transistor are located in the same plane, this fabrication process can be inserted in the current MOS process flow.
摘要翻译：本发明公开了一种用于SOI技术的MOS ESD保护器件和该器件的制造方法。 MOS ESD保护器件包括：在SOI衬底的顶部上生长的外延硅层; 设置在所述外延硅层的两侧的第一侧壁间隔件，以将所述ESD保护装置与所述固有活性结构隔离; 分别设置在所述外延硅层的两侧的源极区域和漏极区域; 形成在外延硅层顶部的多晶硅栅极和栅极电介质; 以及设置在多晶硅栅极两侧的第二侧壁间隔物。 ESD泄漏电流通过SOI衬底进行保护。由于ESD保护器件和本征MOS晶体管位于同一平面内，所以该制造工艺可以插入当前的MOS工艺流程中。

10. 发明申请

US20150194338A1 Method For Preparing Ultra-thin Material On Insulator Through Adsorption By Doped Ultra-thin Layer 有权
标题翻译：通过掺杂超薄层吸附绝缘体制备超薄材料的方法
公开(公告)号：US20150194338A1
公开(公告)日：2015-07-09
申请号：US13825079
申请日：2012-09-25
申请人： Zengfeng Di , Da Chen , Jiantao Bian , Zhongying Xue , Miao Zhang
发明人： Zengfeng Di , Da Chen , Jiantao Bian , Zhongying Xue , Miao Zhang
IPC分类号： H01L21/762 , H01L21/306
CPC分类号： H01L21/76254 , H01L21/30604 , H01L21/30625
摘要： The present invention provides a method for preparing an ultra-thin material on insulator through adsorption by a doped ultra-thin layer. In the method, first, an ultra-thin doped single crystal film and an ultra-thin top film (or contains a buffer layer) are successively and epitaxially grown on a first substrate, and then a high-quality ultra-thin material on insulator is prepared through ion implantation and a bonding process. A thickness of the prepared ultra-thin material on insulator ranges from 5 nm to 50 nm. In the present invention, the ultra-thin doped single crystal film adsorbs the implanted ion, and a micro crack is then formed, so as to implement ion-cut; therefore, the roughness of a surface of a ion-cut material on insulator is small. In addition, an impurity atom strengthens an ion adsorption capability of the ultra-thin single crystal film, so that an ion implantation dose and the annealing temperature can be lowered in the preparation procedure, thereby effectively reducing the damage caused by the implantation to the top film, and achieving objectives of improving production efficiency and reducing the production cost.
摘要翻译：本发明提供一种通过掺杂超薄层吸附制备绝缘体上的超薄材料的方法。在该方法中，首先，在第一基板上依次外延生长超薄掺杂单晶膜和超薄顶膜（或包含缓冲层），然后在绝缘体上形成高品质超薄材料通过离子注入和粘合工艺制备。所制备的绝缘体上的超薄材料的厚度范围为5nm至50nm。在本发明中，超薄掺杂单晶膜吸附注入的离子，然后形成微裂纹，从而实现离子切割; 因此，绝缘体上的离子切割材料的表面的粗糙度小。此外，杂质原子增强了超薄单晶膜的离子吸附能力，使得在制备过程中可以降低离子注入剂量和退火温度，从而有效地减少了植入到顶部的损伤电影，实现提高生产效率和降低生产成本的目标。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式