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1. 发明授权

US06784688B2 Skewed repeater bus 失效
公开(公告)号：US06784688B2
公开(公告)日：2004-08-31
申请号：US10334410
申请日：2002-12-30
申请人： Muhammad M. Khellah , James W. Tschanz , Yibin Ye , Vivek K. De
发明人： Muhammad M. Khellah , James W. Tschanz , Yibin Ye , Vivek K. De
IPC分类号： H03K19003
CPC分类号： H04L25/14
摘要： According to some embodiments, provided are a first signal line, the first signal line coupled to a first repeater, the first repeater to convert a first signal from a received signal level to an output signal level, the first repeater to convert from a first signal level to a second signal level slower than from the second signal level to the first signal level, and a second signal line adjacent to the first signal line, the second signal line coupled to a second repeater adjacent to the first repeater, the second repeater to convert a second signal from a second received signal level to a second output signal level, the second repeater to convert from the first signal level to the second signal level slower than from the second signal level to the first signal level, wherein the received signal level is substantially equivalent to the second output signal level and wherein the second received signal level is substantially equivalent to the output signal level.

2. 发明授权

US07684520B2 Method and apparatus for bus repeater tapering 有权
标题翻译：总线中继器渐变的方法和装置
公开(公告)号：US07684520B2
公开(公告)日：2010-03-23
申请号：US10334746
申请日：2002-12-31
申请人： James W. Tschanz , Muhammad M. Khellah , Yibin Ye , Vivek K. De
发明人： James W. Tschanz , Muhammad M. Khellah , Yibin Ye , Vivek K. De
IPC分类号： H04L27/00
CPC分类号： H04L25/242
摘要： A method and apparatus for bus repeater tapering. The sizing of repeaters on a portion of one transmission line is chosen to propagate a signal transition at a particular rate. The sizing of repeaters on a substantially parallel portion of another transmission line, is chosen to propagate a second signal transition at a different rate. Thus, the worst-case capacitance coupling factor between the two transmission lines may be reduced.
摘要翻译：一种用于总线中继器锥形化的方法和装置。选择一个传输线路的一部分上的中继器的大小以传播特定速率的信号转换。选择在另一传输线的基本平行部分上的中继器的尺寸以便以不同的速率传播第二信号转换。因此，可以减小两条传输线之间的最坏情况电容耦合系数。

3. 发明授权

US07423899B2 SRAM device having forward body bias control 有权
标题翻译：具有前向偏置控制的SRAM器件
公开(公告)号：US07423899B2
公开(公告)日：2008-09-09
申请号：US10812894
申请日：2004-03-31
申请人： Stephen H. Tang , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De , James W. Tschanz
发明人： Stephen H. Tang , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De , James W. Tschanz
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C11/412
摘要： A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inverter configuration so as to apply a forward body bias to the PMOS transistors of the cross-coupled inverter configuration. A power control unit may control a supply voltage to each of the PMOS transistors as well as apply the switching signal to the NMOS transistor based on a STANDBY mode of the memory cell.
摘要翻译：提供具有多个存储单元的SRAM器件。每个存储单元可以包括以交叉耦合的反相器配置耦合的多个晶体管。 NMOS晶体管可以以交叉耦合的反相器配置耦合到两个PMOS晶体管的主体，以便向交叉耦合的反相器配置的PMOS晶体管施加正向偏置。功率控制单元可以控制每个PMOS晶体管的电源电压，并且基于存储器单元的STANDBY模式将开关信号施加到NMOS晶体管。

4. 发明授权

US07342845B2 Method and apparatus to clamp SRAM supply voltage 有权
标题翻译： SRAM电源电压的方法和装置
公开(公告)号：US07342845B2
公开(公告)日：2008-03-11
申请号：US11320789
申请日：2005-12-30
申请人： Dinesh Somasekhar , Muhammad M. Khellah , Yibin Ye , Vivek K. De , James W. Tschanz , Stephen H. Tang
发明人： Dinesh Somasekhar , Muhammad M. Khellah , Yibin Ye , Vivek K. De , James W. Tschanz , Stephen H. Tang
IPC分类号： G11C7/00
CPC分类号： G11C5/143 , G11C5/147 , G11C11/413
摘要： An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.
摘要翻译：提供了一种用于限制SRAM装置中的电源电压下降以保持IDLE状态期间存储器的状态的装置和方法。该装置可以包括存储器阵列，睡眠装置和钳位电路。钳位电路可以被配置为当存储器阵列上的电压降低于预设电压并且存储器阵列处于空闲状态时激活睡眠装置。

5. 发明授权

US07326972B2 Interconnect structure in integrated circuits 有权
标题翻译：集成电路中的互连结构
公开(公告)号：US07326972B2
公开(公告)日：2008-02-05
申请号：US10880988
申请日：2004-06-30
申请人： Maged M. Ghoneima , Muhammad M. Khellah , James W. Tschanz , Yibin Ye , Vivek K. De
发明人： Maged M. Ghoneima , Muhammad M. Khellah , James W. Tschanz , Yibin Ye , Vivek K. De
IPC分类号： H01L27/10
CPC分类号： G06F13/4217 , G11C7/1048 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A device includes an interconnect structure having a number of circuit paths to transfer signals. The circuit paths transfer the signals at different speed to reduce the coupling capacitance effect between adjacent circuit paths.
摘要翻译：一种器件包括具有多个用于传输信号的电路路径的互连结构。电路路径以不同的速度传送信号，以减少相邻电路路径之间的耦合电容效应。

6. 发明授权

US07307899B2 Reducing power consumption in integrated circuits 有权
标题翻译：降低集成电路的功耗
公开(公告)号：US07307899B2
公开(公告)日：2007-12-11
申请号：US11134450
申请日：2005-05-23
申请人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De , James W. Tschanz , Stephen H. Tang
发明人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De , James W. Tschanz , Stephen H. Tang
IPC分类号： G11C7/00 , G11C11/00 , G11C7/10 , G11C8/00
CPC分类号： G11C5/14 , G11C8/12
摘要： A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors.
摘要翻译：提供了一种降低集成存储器件功耗的方法和装置。存储单元组可以通过相应的“睡眠”晶体管单独地进入“睡眠”模式。

7. 发明授权

US07183795B2 Majority voter apparatus, systems, and methods 失效
标题翻译：多数选民设备，制度和方法
公开(公告)号：US07183795B2
公开(公告)日：2007-02-27
申请号：US10947765
申请日：2004-09-23
申请人： Yibin Ye , James W. Tschanz , Muhammad M. Khellah , Vivek K. De
发明人： Yibin Ye , James W. Tschanz , Muhammad M. Khellah , Vivek K. De
IPC分类号： H03K19/23
CPC分类号： H03K19/23
摘要： Apparatus and systems, as well as methods and articles, may operate to provide a majority voter indication using a sense amplifier coupled to a first plurality of bit inputs and to a second plurality of bit inputs.
摘要翻译：装置和系统以及方法和物品可以使用耦合到第一多个位输入和第二多个位输入的读出放大器来提供多数选举指示。

8. 发明授权

US07020041B2 Method and apparatus to clamp SRAM supply voltage 有权
标题翻译： SRAM电源电压的方法和装置
公开(公告)号：US07020041B2
公开(公告)日：2006-03-28
申请号：US10738216
申请日：2003-12-18
申请人： Dinesh Somasekhar , Muhammad M. Khellah , Yibin Ye , Vivek K. De , James W. Tschanz , Stephen H. Tang
发明人： Dinesh Somasekhar , Muhammad M. Khellah , Yibin Ye , Vivek K. De , James W. Tschanz , Stephen H. Tang
IPC分类号： G11C7/00
CPC分类号： G11C5/143 , G11C5/147 , G11C11/413
摘要： An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.
摘要翻译：提供了一种用于限制SRAM装置中的电源电压下降以保持IDLE状态期间存储器的状态的装置和方法。该装置可以包括存储器阵列，睡眠装置和钳位电路。钳位电路可以被配置为当存储器阵列上的电压降低于预设电压并且存储器阵列处于空闲状态时激活睡眠装置。

9. 发明授权

US07236005B1 Majority voter circuit design 有权
标题翻译：多数选民电路设计
公开(公告)号：US07236005B1
公开(公告)日：2007-06-26
申请号：US11053788
申请日：2005-02-09
申请人： Yibin Yee , James W. Tschanz , Muhammad M. Khellah , Vivek K. De
发明人： Yibin Yee , James W. Tschanz , Muhammad M. Khellah , Vivek K. De
IPC分类号： H03K19/23 , H03K19/003 , H03K19/20
CPC分类号： H03K19/23
摘要： A method and apparatus for performing majority voting is presented. The method selects pairs of inputs, performs AND and NOR operations on each pair of inputs to determine that each pair of inputs is both high or both low, yielding a quantity of “both high” pairs and a quantity of “both low” pairs, and compares the quantity of “both high” pairs against the quantity of “both low” pairs to determine the majority. The apparatus includes AND gates configured to receive pairs of values and NOR gates configured to receive the same pairs of values, with a connections between all AND gates and connections between all NOR gates. A summation element sums all AND gate outputs and all NOR gate outputs to determine the majority.
摘要翻译：提出了一种执行多数投票的方法和装置。该方法选择输入对，对每对输入进行AND和NOR运算，以确定每对输入均为高电平或两者均为低电平，产生“两高”对数量和“两低” 并将“两高”对数与“两低”对的数量进行比较，以确定多数。该装置包括被配置为接收配对的值对和配置成接收相同的值对的与非门，其中所有与门之间的连接和所有NOR门之间的连接。求和元素将所有与门输出和所有NOR门输出相加以确定大多数。

10. 发明授权

US09230636B2 Apparatus for dual purpose charge pump 有权
标题翻译：双用电荷泵装置
公开(公告)号：US09230636B2
公开(公告)日：2016-01-05
申请号：US14137808
申请日：2013-12-20
申请人： Pascal A. Meinerzhagen , Jaydeep P. Kulkarni , Muhammad M. Khellah , Cyrille Dray , Dinesh Somasekhar , James W. Tschanz , Vivek K. De
发明人： Pascal A. Meinerzhagen , Jaydeep P. Kulkarni , Muhammad M. Khellah , Cyrille Dray , Dinesh Somasekhar , James W. Tschanz , Vivek K. De
IPC分类号： G11C5/14 , G11C11/4074 , G11C11/16 , G11C16/06 , G11C11/406 , G11C11/4076 , G11C5/06 , G11C11/408
CPC分类号： G11C11/4074 , G11C5/063 , G11C5/14 , G11C5/145 , G11C5/148 , G11C11/1697 , G11C11/406 , G11C11/4076 , G11C11/4085 , G11C11/4087 , G11C11/417 , G11C16/06
摘要： Described is an apparatus which comprises: a first power supply node to provide a first power supply, a second power supply node, and a third power supply node; a first transistor which is operable to couple the first and second power supply nodes; and a charge pump circuit to provide a boosted voltage to the third power supply node in one mode, and to recover charge from the second power node in another mode. Described is a memory unit which comprises: a DRAM which is operable to be refreshed; a gated power supply node coupled to the DRAM to provide a gated power supply to the DRAM; and a charge recycling circuit to recover charge from the gated power supply node after the DRAM is refreshed.
摘要翻译：描述了一种装置，包括：提供第一电源的第一电源节点，第二电源节点和第三电源节点; 第一晶体管，其可操作以耦合所述第一和第二电源节点; 以及电荷泵电路，以一种模式向第三电源节点提供升压电压，并且在另一模式下从第二功率节点恢复电荷。描述了一种存储单元，其包括：可操作以刷新的DRAM; 门极电源节点，其耦合到DRAM以向DRAM提供门控电源; 以及充电回收电路，用于在DRAM被刷新之后从门控电源节点恢复电荷。

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