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1. 发明授权

US06724217B2 CMOS output amplifier independent of temperature, supply voltage and manufacturing quality of transistors 失效
标题翻译： CMOS输出放大器独立于温度，电源电压和晶体管的制造质量
公开(公告)号：US06724217B2
公开(公告)日：2004-04-20
申请号：US10150832
申请日：2002-05-17
申请人： Steven M. Labram , Guy Mabboux
发明人： Steven M. Labram , Guy Mabboux
IPC分类号： H03K19003
CPC分类号： H03K3/0315 , H03K19/00384 , H03L1/00 , H03L7/0997
摘要： The invention relates to a circuit of which the operating rate varies according to temperature, supply voltage and intrinsic quality of the transistors of the circuit, associated to a compensating circuit which comprises a constant current source (26) that produces a substantially constant current which is independent of temperature, supply voltage and intrinsic quality of the transistors of the circuit, a variable current source (28) producing a current that increases in an inverse proportion to temperature, supply voltage and intrinsic quality of the transistors of the circuit, and means for decreasing the operating rate of the circuit when the difference of the currents produced by the first and second sources increases.
摘要翻译：本发明涉及一种电路，其工作速率根据包括恒定电流源（26）的补偿电路所关联的电路晶体管的温度，电源电压和固有质量而变化，补偿电路产生基本上恒定的电流，独立于电路的晶体管的温度，电源电压和固有质量，产生与电路的晶体管的温度，电源电压和固有质量成反比的电流的可变电流源（28），以及用于当由第一和第二源产生的电流的差增加时，降低电路的工作速率。

2. 发明授权

US06670822B2 Transceiver driver with programmable edge rate control independent of fabrication process, supply voltage, and temperature 失效
标题翻译：收发器驱动器，具有可编程边沿速率控制，独立于制造工艺，电源电压和温度
公开(公告)号：US06670822B2
公开(公告)日：2003-12-30
申请号：US09132595
申请日：1998-08-11
申请人： Oscar W. Freitas
发明人： Oscar W. Freitas
IPC分类号： H03K19003
CPC分类号： H03K19/00361 , H03K19/00384
摘要： A transceiver driver for shaping an output signal includes one or more capacitive elements designed to manipulate the current applied to the control node of the driver's output transistor. The capacitive elements may be one or more capacitors coupled to an inverter branch that provides turn-on and turn-off potential to the gate of the output transistor. The capacitive elements act to charge or discharge the transistor's gate gradual in a highly programmable way so as to make the driver substantially independent of fabrication, supply voltage, and operating temperature vagaries.
摘要翻译：用于整形输出信号的收发器驱动器包括被设计成操纵施加到驱动器输出晶体管的控制节点的电流的一个或多个电容元件。电容元件可以是耦合到反相器支路的一个或多个电容器，其向输出晶体管的栅极提供导通和关断电位。电容元件用于以高度可编程的方式对晶体管栅极进行逐步放电或放电，以使驱动器基本上与制造，电源电压和工作温度变化无关。

3. 发明授权

US06664805B2 Switched capacitor piecewise linear slew rate control methods for output devices 失效
标题翻译：用于输出设备的开关电容器分段线性压摆率控制方法
公开(公告)号：US06664805B2
公开(公告)日：2003-12-16
申请号：US10060535
申请日：2002-01-30
申请人： Jason Gonzalez
发明人： Jason Gonzalez
IPC分类号： H03K19003
CPC分类号： H03K17/166 , H03K17/164
摘要： A novel method and apparatus is presented for reducing the slew rate signals on transmission lines of integrated circuits by stepwise ramping up or down the voltage level on the transmission line. Switched capacitors or current sources are connected to either directly to the transmission line itself, or to the control input of a driver device characterized by a linear region during which the output voltage on the transmission line is proportional to the voltage seen at the control input.
摘要翻译：提出了一种新颖的方法和装置，用于通过逐步斜升传输线上的电压电平来减小集成电路的传输线上的转换速率信号。开关电容器或电流源直接连接到传输线本身或连接到以线性区域为特征的驱动器器件的控制输入端，在该线性区域期间，传输线上的输出电压与在控制输入处看到的电压成比例。

4. 发明授权

US06614257B2 Logic architecture for single event upset immunity 失效
公开(公告)号：US06614257B2
公开(公告)日：2003-09-02
申请号：US09854247
申请日：2001-05-11
申请人： Kenneth R. Knowles
发明人： Kenneth R. Knowles
IPC分类号： H03K19003
CPC分类号： H03K19/00338 , H03K19/0075
摘要： An SEU immune logic architecture includes a dual path logic gate coupled to a dual to single path converter. A first and a second logic element within the dual path logic gate are functionally and possibly structurally equivalent, and are coupled to receive input signals spanning redundant input signal sets. A given logic structure within the first logic element may receive specified input signals within a particular input signal set, while an analogous logic structure within the second logic element may receive corresponding input signals within the counterpart input signal set. A radiation induced transient pulse that affects one input signal may affect an output signal asserted by one logic structure; however, since the transient pulse doesn't affect a corresponding input signal applied to the analogous logic structure, the dual path logic gate may output at least one correctly valued signal when a transient pulse occurs. The dual to single path converter is coupled to receive signals output by the dual path logic gate. In the event that a transient signal appears at an input of the dual to single path converter, a current path may be interrupted, and a correct output signal value is maintained as a result of stray capacitance present at an output node.

5. 发明授权

US06580287B2 Voltage-boosting generator for reducing effects due to operating voltage variation and temperature change 有权
标题翻译：电压升压发生器，用于减少由于工作电压变化和温度变化引起的影响
公开(公告)号：US06580287B2
公开(公告)日：2003-06-17
申请号：US10099806
申请日：2002-03-13
申请人： Hsien-Wen Hsu , Yu-Shen Lin , Chun-Hsiung Hung , Ho-Chun Liou
发明人： Hsien-Wen Hsu , Yu-Shen Lin , Chun-Hsiung Hung , Ho-Chun Liou
IPC分类号： H03K19003
CPC分类号： H02M3/07
摘要： A voltage-boosting generator for reducing the effects due to operating voltage variation and temperature change. The generator comprises a delay line circuit and a voltage boosting circuit. The delay line circuit is used to perform a time delay according to an initial boosting signal and to produce a control signal. The voltage boosting circuit is used to boosted voltage according to the control signal.
摘要翻译：一种电压升压发生器，用于降低由于工作电压变化和温度变化引起的影响。发电机包括延迟线电路和升压电路。延迟线电路用于根据初始升压信号执行时间延迟并产生控制信号。升压电路根据控制信号用于升压。

6. 发明授权

US06486697B1 Line reflection reduction with energy-recovery driver 失效
标题翻译：能量回收驱动线路反射减少
公开(公告)号：US06486697B1
公开(公告)日：2002-11-26
申请号：US09532798
申请日：2000-03-21
申请人： Lars G. Svensson , William C. Athas
发明人： Lars G. Svensson , William C. Athas
IPC分类号： H03K19003
CPC分类号： H04L25/028 , H03K3/00 , H03K17/00 , H03K19/0005 , H03K19/0019 , H04L25/0278 , H04L25/0286 , H04L25/0298
摘要： A system and method for reducing reflections in a transmission line and for recovering energy from the load in the transmission during the process. At least three drive signal levels are utilized. The transition from the second level to the third level during a rising transition and the transition from the second. level to the first level during a falling transition is timed to coincide with the arrival of the reflected signal from the immediately preceding transition. A capacitor is advantageously used as the source for the intermediate drive signal levels and advantageously facilitates energy recovery and conservation.
摘要翻译：一种用于减少传输线中的反射并且在该过程期间从传输中的负载中恢复能量的系统和方法。至少使用三个驱动信号电平。在上升的过渡期间从第二级到第三级的过渡以及从第二级到第三级的过渡。在下降转换期间的电平达到第一电平的时间与来自紧接在前的转换的反射信号的到达相一致。有利地，电容器用作中间驱动信号电平的源，并且有利地有助于能量回收和保存。

7. 发明授权

US06456114B1 Power conserving CMOS semiconductor integrated circuit 失效
标题翻译：省电CMOS半导体集成电路
公开(公告)号：US06456114B1
公开(公告)日：2002-09-24
申请号：US09861647
申请日：2001-05-22
申请人： Chizuru Inoshita , Kazuo Aoki , Toshinori Inoshita
发明人： Chizuru Inoshita , Kazuo Aoki , Toshinori Inoshita
IPC分类号： H03K19003
CPC分类号： H03K19/00323
摘要： A semiconductor integrated circuit device includes a control circuit for coping with time differences in signals propagating along by differences in routes of the circuit device. In a definite data interval when changes of all signals have been completed, the control circuit outputs a received signal. In an indefinite data interval when changes of all signals have not been completed, the control circuit outputs a fixed signal irrespective of signal level of a received signal. The control circuit thus prevents irregular signal changes caused by the time differences before definition of data to subsequent circuits.
摘要翻译：一种半导体集成电路器件，包括控制电路，用于应对沿着电路器件的路径差异传播的信号中的时间差。在完成所有信号的改变的确定的数据间隔中，控制电路输出接收的信号。在所有信号的改变尚未完成的无限数据间隔中，控制电路输出固定信号，而与接收信号的信号电平无关。因此，控制电路防止在将数据定义为后续电路之前的时间差引起的不规则信号变化。

8. 发明授权

US06445091B1 Integrated semiconductor circuit having at least two supply networks 失效
标题翻译：具有至少两个供电网络的集成半导体电路
公开(公告)号：US06445091B1
公开(公告)日：2002-09-03
申请号：US09197369
申请日：1998-11-20
申请人： Martin Buck
发明人： Martin Buck
IPC分类号： H03K19003
CPC分类号： G11C5/14 , H03K19/018521 , Y10T307/858
摘要： An integrated semiconductor circuit has at least two supply networks that are supplied independently of one another. The two supply networks include a first, load supply network, which is associated with a load circuit, and a second, driver supply network, which is associated with a driver circuit. Each supply network has a ground path with ground lines and a supply path with supply potential lines which are separate from the ground path. A compensating circuit is provided which alternatively couples the ground paths and/or the supply paths of the at least two supply networks to one another.
摘要翻译：集成半导体电路具有彼此独立地提供的至少两个供电网络。两个供电网络包括与负载电路相关联的第一负载供应网络和与驱动器电路相关联的第二驱动器供电网络。每个供电网络具有接地线的接地路径和具有与接地路径分开的供电电位线的供电路径。提供补偿电路，其将至少两个供电网络的接地路径和/或供电路径交替地彼此耦合。

9. 发明授权

US06420896B1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06420896B1
公开(公告)日：2002-07-16
申请号：US09827928
申请日：2001-04-09
申请人： Hideshi Maeno
发明人： Hideshi Maeno
IPC分类号： H03K19003
CPC分类号： G11C29/48 , G11C2029/3202
摘要： To provide a semiconductor integrated circuit having a redundancy-relieved data output function which can carry out a pass/fail test of a selecting operation of a redundancy-relieved output selecting circuit for redundancy-relieved output data. Data inputs D of scan flip-flops SFFC , SFFC , SFFC and SFFC are connected to redundancy-relieved output data XDO , XDO , XDO and XDO in place of output data DO , DO , DO and DO of a conventional RAM 211, respectively. An AND gate 21 receives a serial output SO at one of inputs and receives a selector test signal PFIN at the other input, and an output thereof is sent to the other input of an AND gate 223. AND gates 221 to 223 to be connected in series receive serial outputs SO to SO of the SFFC to the SFFC at inputs, respectively.
摘要翻译：提供一种具有冗余度减小的数据输出功能的半导体集成电路，该功能可执行用于冗余消除输出数据的冗余缓冲输出选择电路的选择操作的通过/失败测试。扫描触发器SFFC ，SFFC ，SFFC 和SFFC i的数据输入D连接到冗余释放输出数据XDO i + 3，XDO < i + 2>，XDO 和XDO i代替常规RAM的输出数据DO ，DO ，DO 和DO 211。 AND门21在其中一个输入端接收串行输出SO 的SO 到输入端的SFFC 的串行输出SO 。

10. 发明授权

US06344755B1 Programmable logic device with redundant circuitry 有权
标题翻译：具有冗余电路的可编程逻辑器件
公开(公告)号：US06344755B1
公开(公告)日：2002-02-05
申请号：US09691424
申请日：2000-10-18
申请人： Srinivas T. Reddy , Manuel Mejia , Andy L. Lee , Bruce B. Pedersen
发明人： Srinivas T. Reddy , Manuel Mejia , Andy L. Lee , Bruce B. Pedersen
IPC分类号： H03K19003
CPC分类号： H03K19/17764 , H03K19/17736
摘要： A programmable logic device is provided that allows a redundant row of programmable logic to be shifted into place to repair the device when a defect is detected in a row of programmable logic on the device. The redundant row is shifted into place by routing programming data into the normal logic and the redundant logic while bypassing the row of logic containing the defect. Switching circuitry may be used to direct programming data into the serial inputs of various data registers that are then used to load the programming data into the device. The patterns of programmable connections that are made between programmable logic regions on the device and vertical and horizontal conductors also allow redundant logic to be shifted into place. Some connections between the logic and the horizontal and vertical conductors may be identical within a column to facilitate shifting. Other connections may only partially overlap between respective rows. The partially overlapping pattern allows the connections to be less regular, which increases flexibility when routing signals on the device.
摘要翻译：提供了一种可编程逻辑器件，其允许在器件上的可编程逻辑行中检测到缺陷时将冗余的可编程逻辑行移位到位以修复器件。通过将编程数据路由到正常逻辑和冗余逻辑中来绕过包含缺陷的逻辑行，将冗余行移位到位。开关电路可用于将编程数据引导到各种数据寄存器的串行输入，然后将其用于将编程数据加载到器件中。在设备上的可编程逻辑区域和垂直和水平导体之间进行的可编程连接的模式也允许将冗余逻辑移位到位。逻辑和水平和垂直导体之间的一些连接可以在列内相同以便于移动。其他连接可能仅在相应行之间部分重叠。部分重叠的模式允许连接不太规则，这在设备上路由信号时增加灵活性。

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