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    • 9. 发明授权
    • Majority voter circuit design
    • 多数选民电路设计
    • US07236005B1
    • 2007-06-26
    • US11053788
    • 2005-02-09
    • Yibin YeeJames W. TschanzMuhammad M. KhellahVivek K. De
    • Yibin YeeJames W. TschanzMuhammad M. KhellahVivek K. De
    • H03K19/23H03K19/003H03K19/20
    • H03K19/23
    • A method and apparatus for performing majority voting is presented. The method selects pairs of inputs, performs AND and NOR operations on each pair of inputs to determine that each pair of inputs is both high or both low, yielding a quantity of “both high” pairs and a quantity of “both low” pairs, and compares the quantity of “both high” pairs against the quantity of “both low” pairs to determine the majority. The apparatus includes AND gates configured to receive pairs of values and NOR gates configured to receive the same pairs of values, with a connections between all AND gates and connections between all NOR gates. A summation element sums all AND gate outputs and all NOR gate outputs to determine the majority.
    • 提出了一种执行多数投票的方法和装置。 该方法选择输入对,对每对输入进行AND和NOR运算,以确定每对输入均为高电平或两者均为低电平,产生“两高”对数量和“两低” 并将“两高”对数与“两低”对的数量进行比较,以确定多数。 该装置包括被配置为接收配对的值对和配置成接收相同的值对的与非门,其中所有与门之间的连接和所有NOR门之间的连接。 求和元素将所有与门输出和所有NOR门输出相加以确定大多数。