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1. 发明授权

US5981404A Multilayer ONO structure 失效
标题翻译：多层ONO结构
公开(公告)号：US5981404A
公开(公告)日：1999-11-09
申请号：US857734
申请日：1997-05-16
申请人： Yi Chung Sheng , Yi Chih Lim , Ming Hua Liu , Ming-Tzong Yang
发明人： Yi Chung Sheng , Yi Chih Lim , Ming Hua Liu , Ming-Tzong Yang
IPC分类号： H01L21/28 , H01L21/314 , H01L29/51 , H01L29/68
CPC分类号： H01L21/28202 , H01L21/28238 , H01L21/3145 , H01L29/513 , H01L29/518 , Y10S438/954
摘要： Dielectric structures of the type that might be used in DRAMs, other memory devices, and integrated thin film transistors include repeated silicon oxide/silicon nitride layers. For example, the dielectric structure may have a silicon oxide/silicon nitride/silicon oxide/silicon nitride/silicon oxide or "ONONO" layer structure. Such repeated layer structures exhibit higher levels of breakdown voltage than more conventional "ONO" structures. Most of the growth of the five layer ONONO or more complicated dielectric structure can be accomplished in a single furnace through a series of temperature steps performed under different gas ambients. A substrate having a polysilicon lower electrode is introduced to a furnace and a lowest layer of silicon oxide is grown on the polysilicon electrode in an ammonia ambient. A first silicon nitride layer is grown in NH.sub.3 and SiH.sub.2 Cl.sub.2 and then growth of the first silicon nitride layer is interrupted by first altering or stopping the flow of reaction gases and then growing an intermediate silicon oxide layer on the first silicon nitride layer, again in an ammonia ambient. A second silicon nitride layer is then formed by reintroducing the same combination of processing gases. Growth of the second silicon nitride layer is then interrupted, and either additional repetitions of the silicon oxide/silicon nitride layer structure are formed or a surface layer of silicon oxide is grown in a steam or wet oxygen ambient.
摘要翻译：可能用于DRAM，其他存储器件和集成薄膜晶体管的类型的介质结构包括重复的氧化硅/氮化硅层。例如，电介质结构可以具有氧化硅/氮化硅/氧化硅/氮化硅/氧化硅或“ONONO”层结构。这种重复的层结构表现出比更传统的“ONO”结构更高的击穿电压水平。通过在不同气体环境下进行的一系列温度步骤，可以在单个炉中实现五层ONONO或更复杂的电介质结构的大部分生长。将具有多晶硅下电极的基板引入炉中，并且在氨气氛中在多晶硅电极上生长最低层的氧化硅。第一氮化硅层生长在NH 3和SiH 2 Cl 2中，然后通过首先改变或停止反应气体的流动然后在第一氮化硅层上再生长中间氧化硅层，从而中断第一氮化硅层的生长氨气。然后通过重新引入相同的处理气体组合来形成第二氮化硅层。然后中断第二氮化硅层的生长，并且形成氧化硅/氮化硅层结构的附加重复，或者在蒸汽或湿氧环境中生长氧化硅的表面层。

2. 发明授权

US08278733B2 Bonding pad structure and integrated circuit chip using such bonding pad structure 有权
标题翻译：使用这种焊盘结构的焊盘结构和集成电路芯片
公开(公告)号：US08278733B2
公开(公告)日：2012-10-02
申请号：US12729224
申请日：2010-03-22
申请人： Ming-Tzong Yang , Yu-Hua Huang
发明人： Ming-Tzong Yang , Yu-Hua Huang
IPC分类号： H01L23/48 , H01L23/485
CPC分类号： H01L24/05 , H01L23/3171 , H01L23/5227 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2224/45147 , H01L2224/48463 , H01L2224/48824 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01327 , H01L2924/05042 , H01L2924/10253 , H01L2924/14 , H01L2924/19041 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit chip includes a substrate; a topmost metal layer over the substrate; a lower metal layer on or over the substrate and lower than the topmost metal layer; and at least one bonding pad in the lower metal layer.
摘要翻译：集成电路芯片包括基板; 衬底上的最上层的金属层; 在基底上或上方的下金属层，低于最上层的金属层; 以及下金属层中的至少一个接合焊盘。

3. 发明申请

US20120112289A1 SEMICONDUCTOR STRUCTURE WITH MULTI-LAYER CONTACT ETCH STOP LAYER STRUCTURE 有权
标题翻译：具有多层接触蚀刻停止层结构的半导体结构
公开(公告)号：US20120112289A1
公开(公告)日：2012-05-10
申请号：US12940022
申请日：2010-11-04
申请人： Tien-Chang Chang , Jing-Hao Chen , Ming-Tzong Yang
发明人： Tien-Chang Chang , Jing-Hao Chen , Ming-Tzong Yang
IPC分类号： H01L27/092 , H01L23/00
CPC分类号： H01L21/823475 , H01L21/76832 , H01L21/76834 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device structure includes a substrate having a transistor thereon; a multi-layer contact etching stop layer (CESL) structure covering the transistor, the multi-layer CESL structure comprising a first CESL and a second CESL; and a dielectric layer on the second CESL. The first CESL is made of a material different from that of the second CESL, and the second CESL is made of a material different from that of the dielectric layer.
摘要翻译：半导体器件结构包括其上具有晶体管的衬底; 覆盖晶体管的多层接触蚀刻停止层（CESL）结构，包括第一CESL和第二CESL的多层CESL结构; 和第二CESL上的介电层。第一个CESL由与第二个CESL不同的材料制成，而第二个CESL由与电介质层不同的材料制成。

4. 发明申请

US20090160019A1 SEMICONDUCTOR CAPACITOR 审中-公开
标题翻译：半导体电容器
公开(公告)号：US20090160019A1
公开(公告)日：2009-06-25
申请号：US11960950
申请日：2007-12-20
申请人： Ming-Tzong Yang
发明人： Ming-Tzong Yang
IPC分类号： H01L29/00
CPC分类号： H01L29/94 , H01L23/5223 , H01L27/0805 , H01L28/86 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure is provided. The capacitor structure includes a plurality of first conductive lines paralleled disposed in a conductive layer on a substrate, wherein the first conductive lines are isolated to each other in the conductive layer and are grouped into a first electrode group and a second electrode group, an insulating layer formed on the first conductive lines and in the space between the first conductive lines, a second conductive line formed on the insulating layer electrically connected to the first conductive lines of the first electrode group, and a third conductive line formed on the insulating layer electrically connected to the first conductive lines of the second electrode group.
摘要翻译：提供电容器结构。电容器结构包括多个平行布置在基板上的导电层中的第一导电线，其中第一导线在导电层中彼此隔离并分组为第一电极组和第二电极组，绝缘体形成在第一导电线上和第一导线之间的空间中的第一导电线，形成在与第一电极组的第一导电线电连接的绝缘层上的第二导线，以及形成在绝缘层上的第三导线，连接到第二电极组的第一导线。

5. 发明申请

US20090057907A1 INTERCONNECTION STRUCTURE 审中-公开
标题翻译：互连结构
公开(公告)号：US20090057907A1
公开(公告)日：2009-03-05
申请号：US11847335
申请日：2007-08-30
申请人： Ming-Tzong Yang , Tien-Chang Chang
发明人： Ming-Tzong Yang , Tien-Chang Chang
IPC分类号： H01L23/52
CPC分类号： H01L23/525 , H01L23/53214 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnection structure includes an inter-layer dielectric; a topmost copper metal layer inlaid into the inter-layer dielectric; an insulating layer disposed on the inter-layer dielectric and the topmost copper metal layer; a via opening in the insulating layer for exposing a top surface of the topmost copper metal layer, wherein the via opening consists of an inwardly tapered upper via portion and a lower via portion having a substantially vertical sidewall profile; and an aluminum layer filling into the via opening.
摘要翻译：互连结构包括层间电介质; 镶嵌在层间电介质中的最上面的铜金属层; 设置在层间电介质和最上层的铜金属层上的绝缘层; 所述绝缘层中的通孔开口用于暴露最上面的铜金属层的顶表面，其中所述通孔由具有基本上垂直的侧壁轮廓的向内锥形的上通孔部分和下通孔部分组成; 以及填充到通孔中的铝层。

6. 发明申请

US20070257290A1 MEMORY STRUCTURE AND MEMORY DEVICE 审中-公开
标题翻译：存储器结构和存储器件
公开(公告)号：US20070257290A1
公开(公告)日：2007-11-08
申请号：US11778100
申请日：2007-07-16
申请人： Ming-Tzong Yang , Wan-Chun Liao , Sheng-Chin Lee , Hsiao-Lin Chen , Chien-Hao Lee , Shr-Wei Shiu
发明人： Ming-Tzong Yang , Wan-Chun Liao , Sheng-Chin Lee , Hsiao-Lin Chen , Chien-Hao Lee , Shr-Wei Shiu
IPC分类号： H01L29/94
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/1085 , H01L27/10852 , H01L28/84
摘要： A memory structure, a memory device and a manufacturing method thereof are provided. First, a substrate is provided and a dielectric layer is formed over the substrate. Then, a pattern is formed in the dielectric layer. An amorphous silicon layer is formed in the pattern and over the dielectric layer. The amorphous silicon layer is patterned to form an electrode over the pattern. Then, a spacer is formed on the sidewall of the electrode. A selective hemispherical grains (HSGS) layer is formed over the surface of the electrode and the surface of the spacer.
摘要翻译：提供了存储器结构，存储器件及其制造方法。首先，提供衬底并且在衬底上形成电介质层。然后，在电介质层中形成图案。在图案中并在电介质层上形成非晶硅层。图案化非晶硅层以在图案上形成电极。然后，在电极的侧壁上形成间隔物。在电极的表面和间隔物的表面上形成选择性半球状晶粒（HSGS）层。

7. 发明授权

US6020251A Method of forming buried diffusion junctions in conjunction with shallow-trench isolation structures in a semiconductor device 失效
标题翻译：在半导体器件中与浅沟槽隔离结构一起形成掩埋扩散结的方法
公开(公告)号：US6020251A
公开(公告)日：2000-02-01
申请号：US63021
申请日：1998-04-20
申请人： Nai-Chen Peng , Ming-Tzong Yang
发明人： Nai-Chen Peng , Ming-Tzong Yang
IPC分类号： H01L21/762 , H01L21/76 , H01L21/336
CPC分类号： H01L21/76224 , H01L21/76202
摘要： A method is provided for use in a semiconductor fabrication process to form buried diffusion junctions in conjunction with shallow-trench isolation (STI) structures in a semiconductor device. This method features beak-like oxide layers formed to serve as a mask prior to the forming of the STI structures, which can prevent the subsequently formed buried diffusion junctions from being broken up during the process for forming the STI structures. Moreover, sidewall-spacer structures are formed on the sidewalls of a silicon nitride layer used as a mask in the ion-implantation process. This can prevent short-circuits between the buried diffusion junctions when the doped areas are annealed to be transformed into the desired buried diffusion junctions.
摘要翻译：提供了一种在半导体制造工艺中用于在半导体器件中与浅沟槽隔离（STI）结构相结合形成埋入扩散结的方法。该方法具有形成为在形成STI结构之前用作掩模的喙状氧化物层，这可以防止随后形成的掩埋扩散接头在用于形成STI结构的工艺期间被破坏。此外，在离子注入工艺中用作掩模的氮化硅层的侧壁上形成侧壁间隔结构。这可以防止当掺杂区域退火以转化成所需的掩埋扩散结时的掩埋扩散结之间的短路。

8. 发明授权

US5633520A Neuron MOSFET with different interpolysilicon oxide 失效
标题翻译：具有不同的多晶硅氧化物的神经元MOSFET
公开(公告)号：US5633520A
公开(公告)日：1997-05-27
申请号：US667609
申请日：1996-06-21
申请人： Chung-Cheng Wu , Ming-Tzong Yang
发明人： Chung-Cheng Wu , Ming-Tzong Yang
IPC分类号： H01L21/822 , H01L27/115 , H01L27/108 , H01L29/76 , H01L29/788
CPC分类号： H01L27/115 , H01L21/8221 , H01L29/788 , Y10S148/116 , Y10S148/117 , Y10S148/163 , Y10S438/981
摘要： An MOSFET device is fabricated with a plurality of conductors capacitively coupled to a first electrode, forming a mask on the surface of the first electrode exposing a predetermined zone of the first electrode, doping the first electrode through the mask, removing the mask from the surface of the first electrode, oxidizing the first electrode to form a layer of oxide over the first electrode with a thicker layer of oxide over the predetermined zone and a thinner layer of oxide elsewhere, forming at least one electrode over the first electrode on the thinner layer of oxide outside of the zone and forming at least one other electrode over the first electrode on the thicker layer of oxide inside the zone, whereby the one electrode and the other electrode have substantially different capacitive coupling to the electrode.
摘要翻译：制造具有电容耦合到第一电极的多个导体的MOSFET器件，在第一电极的表面上形成掩模，暴露第一电极的预定区域，通过掩模掺杂第一电极，从表面去除掩模在所述第一电极上氧化所述第一电极以在所述第一电极上形成氧化层以在所述预定区域上具有较厚的氧化物层，并且在其它地方形成更薄的氧化物层，在所述较薄层上的所述第一电极上形成至少一个电极的氧化物，并且在所述区域内的更厚的氧化物层上在所述第一电极上方形成至少一个其它电极，由此所述一个电极和所述另一个电极具有与所述电极基本上不同的电容耦合。

9. 发明授权

US5429971A Method of making single bit erase flash EEPROM 失效
标题翻译：单位擦除闪存EEPROM的方法
公开(公告)号：US5429971A
公开(公告)日：1995-07-04
申请号：US317016
申请日：1994-10-03
申请人： Ming-Tzong Yang
发明人： Ming-Tzong Yang
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： A semiconductor transistor device on a semiconductor substrate comprises source/drain regions in the substrate. A tunnelling oxide layer combined with a gate oxide layer covers the substrate including the heavily doped regions. A pair of floating gates above the tunnelling oxide layer form source/drain relationships with three centrally located ones of the heavily doped regions. A first dielectric layer covers the floating gates. A set of control gates cover the first dielectric layer. A second dielectric layer covers the control gates. The floating gate structure, the first dielectric layer, the control gate layer and the second dielectric layer all forming with the three centrally located heavily doped regions an adjacent pair of stacked EEPROM transistor structures, with two additional, adjacent, outboard heavily doped regions. Spacers cover the tunneling oxide regions covering the second dielectric layer and the sides of the stacked structure, and a select gate line extends over the top of the spacer layer structure and in source/drain relationship with the two additional outboard heavily doped regions and the outer ones of the three centrally located heavily doped regions.
摘要翻译：半导体衬底上的半导体晶体管器件包括衬底中的源极/漏极区域。与栅极氧化物层结合的隧道氧化物层覆盖包括重掺杂区域的衬底。隧道氧化物层上方的一对浮动栅极与三个位于重掺杂区域的中心位置形成源极/漏极的关系。第一介电层覆盖浮动栅极。一组控制栅极覆盖第一介电层。第二介电层覆盖控制门。浮置栅极结构，第一介电层，控制栅极层和第二介电层都与三个位于中心的重掺杂区域形成相邻的一对堆叠的EEPROM晶体管结构，具有两个附加的相邻的外侧重掺杂区域。间隔物覆盖覆盖第二电介质层和层叠结构的侧面的隧穿氧化物区域，并且选择栅极线在间隔层结构的顶部上延伸并且与两个另外的外侧重掺杂区域的源极/漏极关系延伸，并且外部三个中心位置的重掺杂区域中的一个。

10. 发明授权

US5418176A Process for producing memory devices having narrow buried N+ lines 失效
标题翻译：具有窄掩埋N +线的存储器件的制造方法
公开(公告)号：US5418176A
公开(公告)日：1995-05-23
申请号：US197748
申请日：1994-02-17
申请人： Ming-Tzong Yang , Cheng-Han Huang , Chen-Chiu Hsue
发明人： Ming-Tzong Yang , Cheng-Han Huang , Chen-Chiu Hsue
IPC分类号： H01L21/8246
CPC分类号： H01L27/1122
摘要： A process of fabricating a read only memory device (ROM) wherein the buried N+lines have desirable well defined very narrow widths and are closely spaced. In the process, an insulating layer is deposited on the substrate. Openings for the buried N+lines having vertical sidewalls are formed through the insulating layer. Spacer layers are formed on the vertical sidewalls of the openings. Impurities are implanted through the openings. The insulating layers is removed and the substrate is oxidized to form silicon oxide insulation strips over the buried N+implanted regions. Next, the read only memory (ROM) device is completed by fabricating floating gates and overlying control gates between the buried N+lines interconnected by a conductive lines that are orthogonal to the buried N+buried lines.
摘要翻译：一种制造只读存储器件（ROM）的工艺，其中掩埋的N +线具有期望的良好定义非常窄的宽度并且紧密间隔开。在该过程中，绝缘层沉积在衬底上。通过绝缘层形成具有垂直侧壁的埋入N +线的开口。间隔层形成在开口的垂直侧壁上。通过开口植入杂质。绝缘层被去除并且衬底被氧化以在掩埋的N +注入区域上形成氧化硅绝缘条。接下来，通过在与埋置的N +掩埋线正交的导线相互连接的掩埋N +线之间制造浮动栅极和覆盖控制栅极来完成只读存储器（ROM）器件。

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