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1. 发明申请

US20100065943A1 METHOD FOR INCLUDING DECOUPLING CAPACITORS INTO SEMICONDUCTOR CIRCUIT HAVING LOGIC CIRCUIT THEREIN AND SEMICONDUCTOR CIRCUIT THEREOF 审中-公开
标题翻译：将解耦电容器放入具有逻辑电路的半导体电路及其半导体电路的方法
公开(公告)号：US20100065943A1
公开(公告)日：2010-03-18
申请号：US12211832
申请日：2008-09-17
申请人： Tien-Chang Chang , Ming-Tzong Yang , Tao Cheng , Cheng-Hsing Chien , Hsin-Hsin Hsiao
发明人： Tien-Chang Chang , Ming-Tzong Yang , Tao Cheng , Cheng-Hsing Chien , Hsin-Hsin Hsiao
IPC分类号： H01L27/04
CPC分类号： H01L28/40 , H01L27/0629 , H01L27/0811
摘要： A method for including decoupling capacitors into a semiconductor circuit having at least a logic circuit therein, includes: arranging a first decoupling capacitor and a second decoupling capacitor into a first area and a second area around the logic circuit respectively, wherein a gate oxide thickness of the first decoupling capacitor is different from a gate oxide thickness of the second decoupling capacitor.
摘要翻译：一种用于将去耦电容器包括至其中至少具有逻辑电路的半导体电路的方法包括：将第一去耦电容器和第二去耦电容器分别布置在逻辑电路周围的第一区域和第二区域中，其中栅极氧化物厚度第一去耦电容器与第二去耦电容器的栅极氧化物厚度不同。

2. 发明授权

US07671469B2 SiGe device with SiGe-embedded dummy pattern for alleviating micro-loading effect 有权
标题翻译： SiGe器件采用SiGe嵌入式虚拟图案，可减轻微负载效应
公开(公告)号：US07671469B2
公开(公告)日：2010-03-02
申请号：US11967264
申请日：2007-12-31
申请人： Tung-Hsing Lee , Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tien-Chang Chang , Yu-Tung Chang
发明人： Tung-Hsing Lee , Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tien-Chang Chang , Yu-Tung Chang
IPC分类号： H01L23/52
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02658 , H01L21/823412 , H01L21/823418 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe.
摘要翻译：具有用于减轻微负载效应的虚设图形的半导体器件包括其内部区域和外部区域之间具有中间环形区域的半导体衬底; 内部区域中的半导体衬底上的SiGe器件; 以及设置在中间环形区域内的半导体衬底上的多个虚设图案。至少一个虚拟图案包含SiGe。

3. 发明申请

US20090215277A1 DUAL CONTACT ETCH STOP LAYER PROCESS 审中-公开
标题翻译：双重接触蚀刻停止层工艺
公开(公告)号：US20090215277A1
公开(公告)日：2009-08-27
申请号：US12037089
申请日：2008-02-26
申请人： Tung-Hsing Lee , Ming-Tzong Yang , Ching-Chung Ko , Tien-Chang Chang , Yu-Tung Chang
发明人： Tung-Hsing Lee , Ming-Tzong Yang , Ching-Chung Ko , Tien-Chang Chang , Yu-Tung Chang
IPC分类号： H01L21/31
CPC分类号： H01L21/823807 , H01L21/823871 , H01L29/7843
摘要： A dual CESL process includes: (1) providing a substrate having thereon a first device region, a second device region and a shallow trench isolation (STI) region between the first and second device regions; (2) forming a first-stress imparting film with a first stress over the substrate, wherein the first-stress imparting film does not cover the second device region; and (3) forming a second-stress imparting film with a second stress over the substrate, wherein the second-stress imparting film does not cover the first device region, an overlapped boundary between the first- and second-stress imparting films is created directly above the STI region, and wherein the overlapped boundary is placed in close proximity to the second device region in order to induce the first stress to a channel region thereof in a transversal direction.
摘要翻译：双CESL工艺包括：（1）提供其上具有第一和第二器件区域之间的第一器件区域，第二器件区域和浅沟槽隔离（STI）区域的衬底; （2）在所述基板上形成具有第一应力的第一应力赋予膜，其中所述第一应力赋予膜不覆盖所述第二器件区域; 和（3）在基板上形成具有第二应力的第二应力赋予膜，其中第二应力赋予膜不覆盖第一器件区域，直接产生第一和第二施加应力膜之间的重叠边界在STI区域之上，并且其中重叠的边界被放置成紧邻第二器件区域，以便在横向方向上引起其沟道区域的第一应力。

4. 发明申请

US20090166676A1 SIGE DEVICE WITH SIGE-EMBEDDED DUMMY PATTERN FOR ALLEVIATING MICRO-LOADING EFFECT 有权
标题翻译：具有用于识别微载荷效应的信号嵌入式模式的信号装置
公开(公告)号：US20090166676A1
公开(公告)日：2009-07-02
申请号：US11967264
申请日：2007-12-31
申请人： Tung-Hsing Lee , Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tien-Chang Chang , Yu-Tung Chang
发明人： Tung-Hsing Lee , Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tien-Chang Chang , Yu-Tung Chang
IPC分类号： H01L29/78
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02658 , H01L21/823412 , H01L21/823418 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe.
摘要翻译：具有用于减轻微负载效应的虚设图形的半导体器件包括其内部区域和外部区域之间具有中间环形区域的半导体衬底; 内部区域中的半导体衬底上的SiGe器件; 以及设置在中间环形区域内的半导体衬底上的多个虚设图案。至少一个虚拟图案包含SiGe。

5. 发明申请

US20120112289A1 SEMICONDUCTOR STRUCTURE WITH MULTI-LAYER CONTACT ETCH STOP LAYER STRUCTURE 有权
标题翻译：具有多层接触蚀刻停止层结构的半导体结构
公开(公告)号：US20120112289A1
公开(公告)日：2012-05-10
申请号：US12940022
申请日：2010-11-04
申请人： Tien-Chang Chang , Jing-Hao Chen , Ming-Tzong Yang
发明人： Tien-Chang Chang , Jing-Hao Chen , Ming-Tzong Yang
IPC分类号： H01L27/092 , H01L23/00
CPC分类号： H01L21/823475 , H01L21/76832 , H01L21/76834 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device structure includes a substrate having a transistor thereon; a multi-layer contact etching stop layer (CESL) structure covering the transistor, the multi-layer CESL structure comprising a first CESL and a second CESL; and a dielectric layer on the second CESL. The first CESL is made of a material different from that of the second CESL, and the second CESL is made of a material different from that of the dielectric layer.
摘要翻译：半导体器件结构包括其上具有晶体管的衬底; 覆盖晶体管的多层接触蚀刻停止层（CESL）结构，包括第一CESL和第二CESL的多层CESL结构; 和第二CESL上的介电层。第一个CESL由与第二个CESL不同的材料制成，而第二个CESL由与电介质层不同的材料制成。

6. 发明申请

US20090057907A1 INTERCONNECTION STRUCTURE 审中-公开
标题翻译：互连结构
公开(公告)号：US20090057907A1
公开(公告)日：2009-03-05
申请号：US11847335
申请日：2007-08-30
申请人： Ming-Tzong Yang , Tien-Chang Chang
发明人： Ming-Tzong Yang , Tien-Chang Chang
IPC分类号： H01L23/52
CPC分类号： H01L23/525 , H01L23/53214 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnection structure includes an inter-layer dielectric; a topmost copper metal layer inlaid into the inter-layer dielectric; an insulating layer disposed on the inter-layer dielectric and the topmost copper metal layer; a via opening in the insulating layer for exposing a top surface of the topmost copper metal layer, wherein the via opening consists of an inwardly tapered upper via portion and a lower via portion having a substantially vertical sidewall profile; and an aluminum layer filling into the via opening.
摘要翻译：互连结构包括层间电介质; 镶嵌在层间电介质中的最上面的铜金属层; 设置在层间电介质和最上层的铜金属层上的绝缘层; 所述绝缘层中的通孔开口用于暴露最上面的铜金属层的顶表面，其中所述通孔由具有基本上垂直的侧壁轮廓的向内锥形的上通孔部分和下通孔部分组成; 以及填充到通孔中的铝层。

7. 发明授权

US08669619B2 Semiconductor structure with multi-layer contact etch stop layer structure 有权
标题翻译：半导体结构具有多层接触蚀刻停止层结构
公开(公告)号：US08669619B2
公开(公告)日：2014-03-11
申请号：US12940022
申请日：2010-11-04
申请人： Tien-Chang Chang , Jing-Hao Chen , Ming-Tzong Yang
发明人： Tien-Chang Chang , Jing-Hao Chen , Ming-Tzong Yang
IPC分类号： H01L27/092
CPC分类号： H01L21/823475 , H01L21/76832 , H01L21/76834 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device structure includes a substrate having a transistor thereon; a multi-layer contact etching stop layer (CESL) structure covering the transistor, the multi-layer CESL structure comprising a first CESL and a second CESL; and a dielectric layer on the second CESL. The first CESL is made of a material different from that of the second CESL, and the second CESL is made of a material different from that of the dielectric layer.
摘要翻译：半导体器件结构包括其上具有晶体管的衬底; 覆盖晶体管的多层接触蚀刻停止层（CESL）结构，包括第一CESL和第二CESL的多层CESL结构; 和第二CESL上的介电层。第一个CESL由与第二个CESL不同的材料制成，而第二个CESL由与电介质层不同的材料制成。

8. 发明授权

US08138616B2 Bond pad structure 有权
标题翻译：焊盘结构
公开(公告)号：US08138616B2
公开(公告)日：2012-03-20
申请号：US12168161
申请日：2008-07-07
申请人： Tien-Chang Chang , Tao Cheng , Chien-Hui Chuang , Bo-Shih Huang
发明人： Tien-Chang Chang , Tao Cheng , Chien-Hui Chuang , Bo-Shih Huang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L23/522 , H01L23/585 , H01L23/60 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01025 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/05042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： A bond pad structure of an integrated circuit includes a conductive pad disposed on a first dielectric layer, a first conductive block formed in a second dielectric layer below the first dielectric layer and electrically connected to the conductive pad through a first via plug formed in the first dielectric layer, and an electrically floating first conductive plate situated under the conductive pad.
摘要翻译：集成电路的接合焊盘结构包括设置在第一介电层上的导电焊盘，形成在第一电介质层下面的第二电介质层中的第一导电块，并且通过形成在第一电介质层中的第一通孔插塞电连接到导电焊盘电介质层和位于导电垫下方的电浮置的第一导电板。

9. 发明授权

US08587090B2 Die seal ring structure 有权
标题翻译：模具密封圈结构
公开(公告)号：US08587090B2
公开(公告)日：2013-11-19
申请号：US13477746
申请日：2012-05-22
申请人： Tien-Chang Chang , Yu-Hua Huang
发明人： Tien-Chang Chang , Yu-Hua Huang
IPC分类号： H01L23/544
CPC分类号： H01L23/562 , H01L23/564 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a die seal ring structure. The die seal ring structure includes an inner seal ring portion surrounding an integrated circuit region. An outer seal ring portion is surrounded by a scribe line, surrounding the inner seal ring portion, wherein the outer seal ring portion has an outer top metal layer pattern with a first width extending over the inner seal ring portion and connecting to an inner next-to-top metal layer pattern of the inner seal ring portion. A first redistribution pattern is disposed on the outer top metal layer pattern, having a second width which is narrower than the first width. A second redistribution pattern is disposed on the first redistribution pattern. A redistribution passivation layer covers the second redistribution pattern and the inner seal ring portion, wherein the redistribution passivation layer is separated from the scribe line by a second distance.
摘要翻译：本发明提供一种模具密封环结构。模具密封环结构包括围绕集成电路区域的内部密封环部分。外密封环部分由围绕内密封环部分的划线包围，其中外密封环部分具有外顶层金属层图案，第一宽度在内密封环部分上延伸并连接到内密封环部分，内密封环部分的顶层金属层图案。第一再分布图案设置在外顶金属层图案上，具有比第一宽度窄的第二宽度。第二再分布图案设置在第一再分布图案上。再分布钝化层覆盖第二再分配图案和内密封环部分，其中再分布钝化层与划线隔开第二距离。

10. 发明申请

US20100102421A1 INTEGRATED CIRCUIT CHIP WITH SEAL RING STRUCTURE 有权
标题翻译：集成电路芯片采用密封圈结构
公开(公告)号：US20100102421A1
公开(公告)日：2010-04-29
申请号：US12650549
申请日：2009-12-31
申请人： Tien-Chang Chang , Shi-Bai Chen , Tao Cheng , Yu-Hua Huang
发明人： Tien-Chang Chang , Shi-Bai Chen , Tao Cheng , Yu-Hua Huang
IPC分类号： H01L23/58
CPC分类号： H01L23/5225 , H01L23/564 , H01L23/585 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip includes an analog and/or RF circuit block and a seal ring structure surrounding the analog and/or RF circuit block. The seal ring structure comprises a continuous outer seal ring and an inner seal ring, wherein the inner seal ring comprises a gap that is situated in front of the analog and/or RF circuit block.
摘要翻译：集成电路芯片包括模拟和/或RF电路块和围绕模拟和/或RF电路块的密封环结构。密封环结构包括连续的外密封环和内密封环，其中内密封环包括位于模拟和/或RF电路块前面的间隙。

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