专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5358885A Method of manufacturing a field effect transistor with a T-shaped gate electrode and reduced capacitance 失效
标题翻译：制造具有T形栅电极和降低电容的场效应晶体管的方法
公开(公告)号：US5358885A
公开(公告)日：1994-10-25
申请号：US46811
申请日：1993-04-16
申请人： Tomoki Oku , Masayuki Sakai , Yasutaka Kohno
发明人： Tomoki Oku , Masayuki Sakai , Yasutaka Kohno
IPC分类号： H01L21/285 , H01L21/335 , H01L29/423 , H01L21/44
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/42316 , Y10S148/10 , Y10S148/139 , Y10S438/951
摘要： A method of producing a field effect transistor includes depositing a first insulating film and a refractory metal on a semiconductor substrate, forming a first aperture penetrating the first insulating film and the refractory metal film to provide a gate electrode production region, depositing a second insulating film on the refractory metal film, etching the second insulating film in a direction perpendicular to the surface of the substrate leaving portions of the second insulating film on opposite side walls of the first aperture to form a second aperture, defining a gate length, depositing a gate metal, and patterning the gate metal layer, the first insulating film, and the refractory metal film in a prescribed width to form a T-shaped gate structure. During etching the second insulating film, since the refractory metal film serves as a etch stopping layer, the first insulating film is not etched and its thickness remains as deposited. Therefore, the space between the over-hanging portion of the T-shaped gate electrode and the source electrode increases and the gate-to-source capacitance is reduced.
摘要翻译：制造场效应晶体管的方法包括在半导体衬底上沉积第一绝缘膜和难熔金属，形成穿透第一绝缘膜的第一孔和难熔金属膜以提供栅电极生产区，沉积第二绝缘膜在所述难熔金属膜上，在垂直于所述基板的表面的方向上蚀刻所述第二绝缘膜，从而将所述第二绝缘膜的部分留在所述第一孔的相对侧壁上，以形成限定栅极长度的第二孔，金属，并以规定的宽度图案化栅极金属层，第一绝缘膜和难熔金属膜，以形成T形栅极结构。在蚀刻第二绝缘膜期间，由于难熔金属膜用作蚀刻停止层，所以第一绝缘膜不被蚀刻并且其厚度保持沉积。因此，T形栅电极的过悬挂部分与源电极之间的空间增加，并且栅极 - 源极电容减小。

2. 发明授权

US5322806A Method of producing a semiconductor device using electron cyclotron resonance plasma CVD and substrate biasing 失效
标题翻译：使用电子回旋共振等离子体CVD和衬底偏压制造半导体器件的方法
公开(公告)号：US5322806A
公开(公告)日：1994-06-21
申请号：US393950
申请日：1989-08-15
申请人： Yasutaka Kohno , Masayuki Sakai
发明人： Yasutaka Kohno , Masayuki Sakai
IPC分类号： H01L21/31 , H01L21/28 , H01L21/285 , H01L21/316 , H01L21/338 , H01L21/768 , H01L29/812 , H01L21/00 , H01L21/02 , H01L21/265 , H01L21/44
CPC分类号： H01L29/66878 , H01L21/02164 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/31608 , H01L21/76819
摘要： A method of producing a semiconductor device including the steps of depositing a refractory metal gate electrode at a predetermined region of a semi-insulating substrate surface, and thereafter depositing an insulating film at regions other than the gate electrode region, wherein the production of the insulating film is carried out by an electron cyclotron resonance plasma CVD method while applying a high frequency electrical bias to the substrate.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在半绝缘衬底表面的预定区域沉积难熔金属栅极电极，然后在除栅电极区域之外的区域沉积绝缘膜，其中绝缘通过电子回旋共振等离子体CVD法进行膜的同时向基板施加高频电偏压。

3. 发明授权

US5448096A Semiconductor device with reduced stress applied to gate electrode 失效
标题翻译：施加到栅电极的应力减小的半导体器件
公开(公告)号：US5448096A
公开(公告)日：1995-09-05
申请号：US262842
申请日：1994-06-21
申请人： Yasutaka Kohno
发明人： Yasutaka Kohno
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/285 , H01L21/318 , H01L21/338 , H01L23/52 , H01L29/47 , H01L29/812 , H01L29/80 , H01L29/04 , H01L29/84
CPC分类号： H01L29/66878 , H01L29/47 , H01L2224/48091
摘要： In a semiconductor device having a gate electrode and an insulating film covering the gate electrode on a compound semiconductor substrate, the stress in the gate metal and the stress produced by the insulating film on the gate electrode cancel so that threshold voltage is not a function of gate orientation relative to the crystalline directions of the substrate.
摘要翻译：在具有覆盖化合物半导体衬底上的栅电极的栅电极和绝缘膜的半导体器件中，栅极金属中的应力和由栅电极上的绝缘膜产生的应力消除，使得阈值电压不是相对于衬底的晶体方向的栅极取向。

4. 发明授权

US4923823A Method of fabricating a self aligned semiconductor device 失效
标题翻译：制造自对准半导体器件的方法
公开(公告)号：US4923823A
公开(公告)日：1990-05-08
申请号：US248429
申请日：1988-09-23
申请人： Yasutaka Kohno
发明人： Yasutaka Kohno
IPC分类号： H01L21/302 , H01L21/28 , H01L21/3065 , H01L21/338 , H01L29/47 , H01L29/812 , H01L29/872
CPC分类号： H01L29/66878 , Y10S438/951
摘要： A method of producing a semiconductor device, such as a MESFET having a self-aligned gate. A triple layer film is formed on the semiconductor substrate. The lowermost layer is a high melting point metal silicide, the intermediate layer a thin high melting point metal and the upper layer an insulator. The thicknesses and etching rates of the layers are selected such that the thin intermediate metal layer protects the underlying silicide and overlying insulator layers during etching. The three layers are anisotropically etched to produce a well-formed gate structure which is used as a mask in an ion implantation step for forming source and drain regions. A subsequent selective etching process removes the insulator layer (which serves as a dummy gate) exposing the underlying silicide layer on which is deposited a low resistance metal such as gold in a self-aligned fashion thereby to improve the high frequency performance of the device.
摘要翻译：一种半导体器件的制造方法，例如具有自对准栅极的MESFET。在半导体衬底上形成三层膜。最下层是高熔点金属硅化物，中间层是薄的高熔点金属，上层是绝缘体。选择层的厚度和蚀刻速率使得薄的中间金属层在蚀刻期间保护下面的硅化物和上覆的绝缘体层。对这三层进行各向异性蚀刻以产生良好形成的栅极结构，其在用于形成源极和漏极区域的离子注入步骤中用作掩模。随后的选择性蚀刻工艺去除以自对准的方式暴露沉积有诸如金的低电阻金属的底层硅化物层（其用作虚拟栅极），从而提高器件的高频性能。

5. 发明授权

US5496748A Method for producing refractory metal gate electrode 失效
$Method for producing refractory metal gate electrode$
标题翻译：难熔金属栅电极的制造方法
公开(公告)号：US5496748A
公开(公告)日：1996-03-05
申请号：US304852
申请日：1994-09-13
申请人： Ryo Hattori , Yasutaka Kohno
发明人： Ryo Hattori , Yasutaka Kohno
IPC分类号： H01L21/306 , H01L21/285 , H01L21/336 , H01L21/338 , H01L29/417 , H01L29/78 , H01L29/812 , H01L21/265
CPC分类号： H01L29/66863 , H01L21/28587
摘要： A method for producing a refractory metal gate electrode includes forming a patterning mask layer that is dissolved in a solution including hydrogen ions and having an aperture on a semiconductor substrate; forming a gate metal layer having an ionization potential larger than hydrogen on the entire surface of the patterning mask layer; forming a low resistance metal layer of a predetermined configuration having an ionization potential smaller than hydrogen on the gate metal layer; covering at least an upper surface of the low resistance metal layer with a film that has no reductive reaction with a solution including hydrogen ions; and removing the patterning mask layer using a solution including hydrogen ions after patterning the gate metal layer. An electrolytic reaction of a system including the gate metal layer, the low resistance metal layer, and the solution including hydrogen ions is suppressed by a film covering at least an upper surface of the low resistance metal layer, and localized abnormal dissolution of the gate metal when removing the patterning mask layer using the solution including the hydrogen ions is suppressed.
摘要翻译：一种难熔金属栅极电极的制造方法，其特征在于，在半导体基板上形成溶解于包含氢离子并具有孔径的溶液的图案化掩模层，在图案化掩模层的整个表面上形成具有大于氢的电离电位的栅极金属层; 在所述栅极金属层上形成具有小于氢的电离电位的预定结构的低电阻金属层; 用不含与氢离子的溶液还原反应的膜覆盖低电阻金属层的至少上表面; 并且在图案化栅极金属层之后，使用包含氢离子的溶液去除图案化掩模层。包含栅极金属层，低电阻金属层和包含氢离子的溶液的系统的电解反应通过覆盖低电阻金属层的至少上表面的膜和栅极金属的局部异常溶解来抑制当使用包含氢离子的溶液去除图案掩模层时被抑制。

6. 发明授权

US5341015A Semiconductor device with reduced stress on gate electrode 失效
标题翻译：具有减小栅电极应力的半导体器件
公开(公告)号：US5341015A
公开(公告)日：1994-08-23
申请号：US625798
申请日：1990-12-11
申请人： Yasutaka Kohno
发明人： Yasutaka Kohno
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/285 , H01L21/318 , H01L21/338 , H01L23/52 , H01L29/47 , H01L29/812 , H01L29/80 , H01L29/04 , H01L29/84
CPC分类号： H01L29/66878 , H01L29/47 , H01L2224/48091
摘要： In a semiconductor device having a gate electrode and an insulating film covering the gate electrode on a compound semiconductor substrate, the vector sum of the stress in the gate metal and the stress produced by the insulating film on the gate electrode is zero. A production method of a semiconductor device includes producing a gate electrode having the same but opposite stress of an insulating film by sputtering under an adjusted gas pressure a target of WSi.sub.x and depositing an insulating film covering the gate electrode.
摘要翻译：在具有覆盖化合物半导体衬底上的栅电极的栅电极和绝缘膜的半导体器件中，栅极金属中的应力的矢量和由栅电极上的绝缘膜产生的应力为零。半导体器件的制造方法包括通过在调整后的气压下通过溅射在WSix上制造具有与绝缘膜相同但相反的应力的栅电极，并沉积覆盖栅电极的绝缘膜。

7. 发明授权

US5391899A Compound semiconductor device with a particular gate structure 失效
标题翻译：具有特定栅极结构的复合半导体器件
公开(公告)号：US5391899A
公开(公告)日：1995-02-21
申请号：US164998
申请日：1993-12-10
申请人： Yasutaka Kohno
发明人： Yasutaka Kohno
IPC分类号： H01L29/812 , H01L21/285 , H01L21/335 , H01L21/338 , H01L29/778 , H01L29/78 , H01L29/784
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/7783
摘要： A compound semiconductor device includes a plurality of epitaxial compound semiconductor layers including an InGaAs layer as the uppermost layer disposed on a semi-insulating compound semiconductor substrate, a groove penetrating through at least the InGaAs layer, an insulating film disposed on the side surfaces of the groove and having ends extending beyond the groove, a gate electrode disposed in the groove and on the insulating film, and source and drain electrodes on the InGaAs layer at opposite sides of the groove self-aligned with the ends of the insulating film.
摘要翻译：化合物半导体器件包括多个外延化合物半导体层，其包括设置在半绝缘性化合物半导体衬底上的作为最上层的InGaAs层，至少贯穿至少该InGaAs层的沟槽，设置在该半导体衬底的侧面上的绝缘膜凹槽并且具有延伸超过凹槽的端部，设置在凹槽中和绝缘膜上的栅极电极以及与绝缘膜的端部自对准的凹槽的相对侧上的InGaAs层上的源极和漏极。

8. 发明授权

US5250453A Production method of a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5250453A
公开(公告)日：1993-10-05
申请号：US953049
申请日：1992-09-29
申请人： Yasutaka Kohno , Tomoki Oku
发明人： Yasutaka Kohno , Tomoki Oku
IPC分类号： H01L21/033 , H01L21/285 , H01L21/338 , H01L29/08 , H01L29/423 , H01L21/265
CPC分类号： H01L29/66878 , H01L21/0337 , H01L21/28581 , H01L21/28587 , H01L21/28593 , H01L29/0891 , H01L29/42316
摘要： A method for producing a field effect transistor includes depositing an insulating film on an active layer produced in a semiconductor substrate and removing a part of the insulating film, leaving a side wall substantially perpendicular to the substrate. A refractory metal is deposited on the surface of the semiconductor substrate and the insulating film. The refractory metal is removed except for a portion at the side wall of the insulating film to produce a gate electrode. A high dopant concentration region is ion implanted using the insulating film and refractory metal as a mask. The insulating film is removed and an intermediate dopant concentration region is ion implanted using the refractory metal as a mask. A source electrode is produced on the high dopant concentration region and a drain electrode is produced on the intermediate dopant concentration region. The invention may be used to produce asymmetrically doped drain and gate regions and an asymmetrically disposed gate electrode.
摘要翻译：一种场效应晶体管的制造方法，其特征在于，在半导体基板上生成的有源层上淀积绝缘膜，除去绝缘膜的一部分，留下与基板大致垂直的侧壁。难熔金属沉积在半导体衬底和绝缘膜的表面上。除绝缘膜的侧壁部分之外除去难熔金属以产生栅电极。使用绝缘膜和难熔金属作为掩模离子注入高掺杂剂浓度区域。除去绝缘膜，并使用难熔金属作为掩模离子注入中间掺杂剂浓度区域。在高掺杂浓度区域上产生源电极，在中间掺杂剂浓度区域产生漏电极。本发明可用于产生不对称掺杂的漏极和栅极区域以及不对称布置的栅电极。

9. 发明授权

US5093274A Semiconductor device and method for manufacture thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5093274A
公开(公告)日：1992-03-03
申请号：US636702
申请日：1991-01-02
申请人： Yasutaka Kohno
发明人： Yasutaka Kohno
IPC分类号： H01L21/3213 , H01L21/338
CPC分类号： H01L29/66878 , H01L21/32136 , Y10S438/951
摘要： A semiconductor device, such as a MESFET having a self-aligned gate, and a method for production thereof. A triple layer film is formed on the semiconductor substrate, then anisotropically etched to produce a gate structure which is used as a mask in an ion implantation step for forming a source and drain. The triple layer film includes a lower high melting point metal silicide, an upper similar metal silicide and an intermediate high melting point metal layer. The first layer forms a Schottky barrier with the semiconductor substrate and serves as a metal silicide gate. The upper layer serves as a dummy gate. The intermediate metal layer serves to protect the metal silicide layers during the etching step, serves as an etchant stop during removal of the dummy gate, and also serves to protect the Schottky barrier after the device is completed. After removal of the dummy gate, a low resistance metal such as gold is self-alignedly deposited in its place and serves to improve the high frequency performance of the device.
摘要翻译：具有自对准栅极的MESFET等半导体装置及其制造方法。在半导体衬底上形成三层膜，然后进行各向异性蚀刻以产生在用于形成源极和漏极的离子注入步骤中用作掩模的栅极结构。三层膜包括下部高熔点金属硅化物，上部相似的金属硅化物和中间高熔点金属层。第一层与半导体衬底形成肖特基势垒，并用作金属硅化物栅极。上层用作虚拟门。中间金属层用于在蚀刻步骤期间保护金属硅化物层，在去除伪栅极期间用作蚀刻剂停止，并且还用于在器件完成之后保护肖特基势垒。在去除虚拟栅极之后，诸如金的低电阻金属在其位置自对准沉积，并用于提高器件的高频性能。

10. 发明授权

US5548144A Recessed gate field effect transistor 失效
标题翻译：嵌入栅场效应晶体管
公开(公告)号：US5548144A
公开(公告)日：1996-08-20
申请号：US205180
申请日：1994-03-03
申请人： Yasutaka Kohno
发明人： Yasutaka Kohno
IPC分类号： H01L21/338 , H01L27/06 , H01L29/812 , H01L29/80 , H01L31/112
CPC分类号： H01L27/0605 , H01L29/8128
摘要： A high power output semiconductor device having a plurality of FET elements on a semi-insulating semiconductor substrate including a first conductivity type semiconductor layer on the semi-insulating semiconductor substrate, a plurality of source and drain electrodes alternatingly arranged on the semiconductor layer, a plurality of gate electrodes respectively disposed in gate recesses formed by etching respective surface regions of the semiconductor layer between each adjacent source and drain electrodes. The gate recess has a asymmetrical two-stage recess structure having a second bottom surface only at the source side of the recess at a depth between a first bottom surface in contact with the gate electrode and the upper surface of the semiconductor layer and is not in contact with the gate electrode. Therefore, the thickness of the active layer at the source side is increased as compared with that in the one-stage recess structure, with the result that the source resistance is reduced because of an increase in the thickness of the active layer at the source side region while avoiding deterioration of the gate drain breakdown voltage due to an increase in the thickness of the active layer at the drain side region.
摘要翻译：一种在半绝缘半导体衬底上具有多个FET元件的高功率输出半导体器件，包括半绝缘性半导体衬底上的第一导电类型半导体层，交替布置在半导体层上的多个源极和漏极，多个分别设置在通过蚀刻每个相邻的源极和漏极之间的半导体层的各个表面区域形成的栅极凹槽中的栅电极。栅极凹槽具有不对称的两级凹陷结构，其仅在凹陷的源极侧的第二底表面处于与栅电极接触的第一底表面和半导体层的上表面之间的深度处，并且不在与栅电极接触。因此，与一级凹部结构相比，源极侧的有源层的厚度增加，由于源极侧的有源层的厚度增加，源电阻降低区域，同时避免由于漏极侧区域的有源层的厚度增加而导致的栅极漏极击穿电压的劣化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式