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1. 发明授权

US06333932B1 Connectionless communications system, its test method, and intra-station control system 失效
标题翻译：无连接通信系统，其测试方法和站内控制系统
公开(公告)号：US06333932B1
公开(公告)日：2001-12-25
申请号：US08518110
申请日：1995-08-21
申请人： Yasusi Kobayasi , Yoshihiro Watanabe , Hiroshi Nishida , Masami Murayama , Naoyuki Izawa , Yasuhiro Aso , Yoshihiro Uchida , Hiromi Yamanaka , Jin Abe , Yoshihisa Tsuruta , Yoshiharu Kato , Satoshi Kakuma , Shiro Uriu , Noriko Samejima , Eiji Ishioka , Shigeru Sekine , Yoshiyuki Karakawa , Atsushi Kagawa , Mikio Nakayama , Miyuki Kawataka , Satoshi Esaka , Nobuyuki Tsutsui , Fumio Hirase , Atsuko Suzuki , Shouji Kohira , Kenichi Okabe , Takashi Hatano , Yasuhiro Nishikawa , Jun Itoh , Shinichi Araya
发明人： Yasusi Kobayasi , Yoshihiro Watanabe , Hiroshi Nishida , Masami Murayama , Naoyuki Izawa , Yasuhiro Aso , Yoshihiro Uchida , Hiromi Yamanaka , Jin Abe , Yoshihisa Tsuruta , Yoshiharu Kato , Satoshi Kakuma , Shiro Uriu , Noriko Samejima , Eiji Ishioka , Shigeru Sekine , Yoshiyuki Karakawa , Atsushi Kagawa , Mikio Nakayama , Miyuki Kawataka , Satoshi Esaka , Nobuyuki Tsutsui , Fumio Hirase , Atsuko Suzuki , Shouji Kohira , Kenichi Okabe , Takashi Hatano , Yasuhiro Nishikawa , Jun Itoh , Shinichi Araya
IPC分类号： H04Q1104
CPC分类号： H04L5/16 , H04L2012/5628 , H04L2012/5645 , H04L2012/5652 , H04Q11/0478
摘要： The quality and performance of the connectionless communications system are improved. When a BOM is received, the destination address DA of the L3-PDU stored in the payload of the BOM is retrieved, and the tag information is obtained from the DA (S11). The output message identifier MID is reserved (S12), and the tag information and output MID are assigned to the BOM (S13). Then, the tag information and output MID are written to the table. When a COM is received, the tag information and output MID are retrieved using the MID of the COM as a key, and the information is provided for the COM (S31 and S32). When an EOM is received, the tag information and output MID are retrieved using the MID of the EOM as a key, and the information is provided for the EOM (S41 and S42). Then, the output MID is released (S43).
摘要翻译：无连接通信系统的质量和性能得到提高。当接收到BOM时，检索存储在BOM的有效载荷中的L3-PDU的目的地地址DA，并从DA获得标签信息（S11）。输出消息标识符MID被保留（S12），标签信息和输出MID被分配给BOM（S13）。然后，将标签信息和输出MID写入表中。当接收到COM时，使用COM的MID作为密钥检索标签信息和输出MID，并为COM提供信息（S31和S32）。当接收到EOM时，使用EOM的MID作为密钥检索标签信息和输出MID，并且为EOM提供信息（S41和S42）。然后，释放输出MID（S43）。

2. 发明授权

US07551612B2 Intra-station control system for connectionless communications system 失效
标题翻译：无连接通信系统的站内控制系统
公开(公告)号：US07551612B2
公开(公告)日：2009-06-23
申请号：US09277213
申请日：1999-03-26
申请人： Yasusi Kobayashi , Yoshihiro Watanabe , Hiroshi Nishida , Masami Murayama , Naoyuki Izawa , Yasuhiro Aso , Yoshihiro Uchida , Hiromi Yamanaka , Jin Abe , Yoshihisa Tsuruta , Yoshiharu Kato , Satoshi Kakuma , Shiro Uriu , Noriko Samejima , Eiji Ishioka , Shigeru Sekine , Yoshiyuki Karakawa , Atsushi Kagawa , Mikio Nakayama , Miyuki Kawataka , Satoshi Esaka , Nobuyuki Tsutsui , Fumio Hirase , Atsuko Suzuki , Shouji Kohira , Kenichi Okabe , Takashi Hatano , Yasuhiro Nishikawa , Jun Itoh , Shinichi Araya
发明人： Yasusi Kobayashi , Yoshihiro Watanabe , Hiroshi Nishida , Masami Murayama , Naoyuki Izawa , Yasuhiro Aso , Yoshihiro Uchida , Hiromi Yamanaka , Jin Abe , Yoshihisa Tsuruta , Yoshiharu Kato , Satoshi Kakuma , Shiro Uriu , Noriko Samejima , Eiji Ishioka , Shigeru Sekine , Yoshiyuki Karakawa , Atsushi Kagawa , Mikio Nakayama , Miyuki Kawataka , Satoshi Esaka , Nobuyuki Tsutsui , Fumio Hirase , Atsuko Suzuki , Shouji Kohira , Kenichi Okabe , Takashi Hatano , Yasuhiro Nishikawa , Jun Itoh , Shinichi Araya
IPC分类号： H04L12/66
CPC分类号： H04L5/16 , H04L2012/5628 , H04L2012/5645 , H04L2012/5652 , H04Q11/0478
摘要： A switch station including an ATM switch; a memory storing control data for operations of the switch station; an intra-station device, accommodating a subscriber line, performing communication operation on subscriber ATM cell; a control processor generating control information in link access protocol (LAP) format; and an interface unit converting LAP control information into ATM cell to the intra-station device through the ATM switch, wherein the control information is communicated according to LAP, the intra-station device receives the control information and transmits a direct memory access request to obtain control data stored in the memory, the interface unit obtains and converts the data format of the control data into ATM cell to transmit to the intra-station device through the switch, and the intra-station device performs the communication operation on the subscriber ATM cell based on the control data received through the switch.
摘要翻译：包括ATM交换机的交换台; 存储用于所述开关站的操作的控制数据的存储器; 站内设备，容纳用户线路，对用户ATM信元进行通信操作; 控制处理器生成链路接入协议（LAP）格式的控制信息; 以及接口单元，其通过ATM交换机将LAP控制信息转换为ATM信元到站内设备，其中根据LAP传送控制信息，站内设备接收控制信息并发送直接存储器访问请求以获得存储在存储器中的控制数据，接口单元获取控制数据的数据格式并将其转换成ATM信元，通过交换机发送到站内设备，并且站内设备对用户ATM信元进行通信操作基于通过交换机接收的控制数据。

3. 发明授权

US5553066A Data transfer system including exchange 失效
标题翻译：数据传输系统包括交换
公开(公告)号：US5553066A
公开(公告)日：1996-09-03
申请号：US307109
申请日：1994-09-16
申请人： Yoshiharu Kato , Ryouzi Takano , Takashi Nara , Takashi Hatano , Yoshio Morita
发明人： Yoshiharu Kato , Ryouzi Takano , Takashi Nara , Takashi Hatano , Yoshio Morita
IPC分类号： H04J3/16 , H04J3/22 , H04M3/00 , H04Q11/04
CPC分类号： H04J3/1694 , H04J3/1647 , H04J3/22 , H04J3/0626
摘要： A data transfer system including an exchange, wherein the exchange transfers data by sharing a plurality of channels by a time division multiplex mode. In this case, the exchange transfers the data by variably allocating respective time slots to be occupied by the respective channels. That is, it is possible to allot any line speed to any channel and therefore possible to mix signals with different data transfer speeds in the frames. This results in an exchange network with a high degree of freedom of transfer for the subscriber terminal equipment.
摘要翻译：一种包括交换机的数据传输系统，其中所述交换机通过以时分复用模式共享多个信道来传送数据。在这种情况下，交换机通过可变地分配要由相应信道占用的各个时隙来传送数据。也就是说，可以将任何线路速度分配给任何通道，因此可以将不同数据传输速度的信号混合在帧中。这导致用户终端设备具有高传输自由度的交换网络。

4. 发明申请

US20070216444A1 Interface circuit and control method thereof 有权
标题翻译：接口电路及其控制方法
公开(公告)号：US20070216444A1
公开(公告)日：2007-09-20
申请号：US11542149
申请日：2006-10-04
申请人： Yoshiharu Kato
发明人： Yoshiharu Kato
IPC分类号： H03K19/0175
CPC分类号： H03K19/0175
摘要： This invention provides an interface circuit for detecting that a DQS signal from a DDR SDRAM is at an intermediate potential. An interface circuit is connected to at least a signal line which transmits the DQS signal from the DDR SDRAM and reaches an intermediate potential VM when the signal attains an inactive state. The interface circuit has a comparing portion for comparing the potential of the DQS with a threshold potential VREFH which is a potential that is different from the intermediate potential VM.
摘要翻译：本发明提供一种用于检测来自DDR SDRAM的DQS信号处于中间电位的接口电路。接口电路至少连接到从DDR SDRAM发送DQS信号的信号线，并且当信号达到非活动状态时到达中间电位VM。接口电路具有比较部分，用于将DQS的电位与作为不同于中间电位VM的电位的阈值电位VREFH进行比较。

5. 发明授权

US07251766B2 Test method and test circuit for electronic device 有权
标题翻译：电子设备的测试方法和测试电路
公开(公告)号：US07251766B2
公开(公告)日：2007-07-31
申请号：US11198221
申请日：2005-08-08
申请人： Yoshiharu Kato
发明人： Yoshiharu Kato
IPC分类号： G01R31/28 , H03K19/00
CPC分类号： G11C29/025 , G01R31/2853 , G11C29/02 , G11C29/36
摘要： A method of testing an electronic device including first and second semiconductor devices connected to each other with a plurality of bus lines. First, the first semiconductor device supplies a selected one of the bus lines with a first logical output signal. Then, the second semiconductor device acquires a first bus line signal from the selected bus line. The second semiconductor device inverts the first bus line signal to generate a second logical output signal. The second semiconductor device transmits the second logical output signal to the first semiconductor device. The first semiconductor device receives a second bus line signal from the selected bus line. The first semiconductor device compares the first logical output signal and the second bus line signal to detect a connection between the first semiconductor device and the second semiconductor device.
摘要翻译：一种测试电子设备的方法，该电子设备包括用多个总线线路彼此连接的第一和第二半导体器件。首先，第一半导体器件向所选择的总线线路提供第一逻辑输出信号。然后，第二半导体器件从所选择的总线获取第一总线信号。第二半导体器件使第一总线信号反相以产生第二逻辑输出信号。第二半导体器件将第二逻辑输出信号发送到第一半导体器件。第一半导体器件从所选择的总线接收第二总线信号。第一半导体器件比较第一逻辑输出信号和第二总线信号以检测第一半导体器件和第二半导体器件之间的连接。

6. 发明申请

US20070091989A1 Signal interface 有权
标题翻译：信号接口
公开(公告)号：US20070091989A1
公开(公告)日：2007-04-26
申请号：US11583130
申请日：2006-10-19
申请人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
发明人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
IPC分类号： H04L5/16 , H04L25/00
CPC分类号： H04L25/0282 , H04L5/04 , H04L25/0294
摘要： Plural transmitter units generate plural currents corresponding to plural logical values, respectively, and propagate the currents to a common signal line. The common signal line synthesizes the currents generated by the transmitter units, and propagates them to a receiver unit as a synthetic current. The receiver unit restores the logical values the transmitter units generated, in accordance with the synthetic current. The values of the currents the transmitter units generate in correspondence with the logical values each differ, so that the value of the synthetic current can be changed for every combination of logical values. Accordingly, the receiver unit can restore the logical values outputted from the respective transmitter units, based on the synthetic current. That is, employing the common signal line enables signals transmitted from the transmitter units to be simultaneously received. Consequently, the number of signal lines laid between the transmitter units and the receiver unit is reduced.
摘要翻译：多个发射机单元分别产生对应于多个逻辑值的多个电流，并将电流传播到公共信号线。公共信号线合成由发射机单元产生的电流，并将其作为合成电流传播到接收机单元。接收器单元根据合成电流恢复发射机单元产生的逻辑值。发射机单元对应于逻辑值产生的电流值各自不同，使得可以针对逻辑值的每个组合来改变合成电流的值。因此，接收机单元可以基于合成电流来恢复从各个发射机单元输出的逻辑值。也就是说，采用公共信号线使得能够同时接收从发送单元发送的信号。因此，放置在发射机单元和接收机单元之间的信号线的数量减少。

7. 发明授权

US07135882B2 Semiconductor integrated circuit device and control method for the semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件及半导体集成电路器件的控制方法
公开(公告)号：US07135882B2
公开(公告)日：2006-11-14
申请号：US11090661
申请日：2005-03-28
申请人： Yoshiharu Kato
发明人： Yoshiharu Kato
IPC分类号： G01R31/26
CPC分类号： G11C16/20 , G11C29/1201 , G11C29/44 , G11C2029/4402 , H04N5/232 , H04N5/2353
摘要： It is intended to provide a semiconductor integrated circuit device permitting reading of information specific to chips within the mounted chips while restraining the increase in the total number of terminals of the package and enabling the area of circuits required for reading information specific to chips to be made smaller than that according to the prior art, and a control method therefor. The same terminal is used as the external terminal to which the pulse signals are inputted and the external terminal from which the chip-specific information is outputted. Also, the external terminal for inputting/outputting required power supply in the normal operation mode and the external terminal for reading chip-specific information in the information reading mode are used in common. The increase in the number of external terminals can be thereby restrained. Moreover, the counter unit is shared between functional circuits and the comparative decision unit. This can serve to restrain the increase in chip area.
摘要翻译：旨在提供一种半导体集成电路装置，允许读取安装的芯片内的芯片的信息，同时抑制封装的端子总数的增加，并且使得能够制作读取芯片特有的信息所需的电路区域小于根据现有技术的控制方法。使用相同的端子作为输入脉冲信号的外部端子和从其输出芯片特定信息的外部端子。此外，共同使用用于在正常操作模式下输入/输出所需电源的外部端子和用于在信息读取模式中读取芯片特定信息的外部端子。由此可以抑制外部端子的数量的增加。此外，计数器单元在功能电路和比较判定单元之间共享。这可以抑制芯片面积的增加。

8. 发明授权

US07133996B2 Memory device and internal control method therefor 有权
公开(公告)号：US07133996B2
公开(公告)日：2006-11-07
申请号：US10279963
申请日：2002-10-25
申请人： Shinichiro Ikeda , Yoshiharu Kato
发明人： Shinichiro Ikeda , Yoshiharu Kato
IPC分类号： G06F12/06
CPC分类号： G11C11/4076 , G11C11/4074 , G11C11/4087
摘要： A memory device for ensuring efficient access and reduction in current consumption. The memory device includes a plurality of memory cells arranged in accordance with a first address and a second address which define a logical address map indicating a logical shape of the memory array. An address map changing unit is operatively coupled to the memory array, for receiving a first address signal for generating the first address and a second address signal for generating the second address. The address map changing unit is capable of changing the logical address map by altering a part of one of the first address signal and the second address signal.

9. 发明授权

US06942157B2 Data processing system and data processing method 有权
标题翻译：数据处理系统和数据处理方法
公开(公告)号：US06942157B2
公开(公告)日：2005-09-13
申请号：US10241979
申请日：2002-09-11
申请人： Tohru Nozawa , Yoshiharu Kato
发明人： Tohru Nozawa , Yoshiharu Kato
IPC分类号： G06K19/07 , H01L21/822 , H01L27/04 , H01Q1/38 , H05K1/02 , H05K1/18 , G06K19/06
CPC分类号： H05K1/0274 , H01L2223/6677 , H01L2224/16225 , H01L2224/73204 , H01L2924/15311 , H05K1/181 , H05K2201/10734
摘要： An IC chip is provided with a wireless unit for inputting and outputting data by wireless communication, in addition to a logic section, so that the IC chip no longer needs I/O pads, leaving only power supply and ground pads. IC chips can input and output data with one another by wireless communications, which makes it possible to significantly improve the spacing relationships of various chips on a singular or even plurality of substrates.
摘要翻译：除了逻辑部分之外，IC芯片还具有用于通过无线通信输入和输出数据的无线单元，使得IC芯片不再需要I / O焊盘，仅留下电源和接地焊盘。 IC芯片可以通过无线通信彼此输入和输出数据，这使得可以显着地改善单个或甚至多个基板上各种芯片的间隔关系。

10. 发明申请

US20050157585A1 Memory control device and memory control method 有权
标题翻译：内存控制装置和内存控制方式
公开(公告)号：US20050157585A1
公开(公告)日：2005-07-21
申请号：US10853313
申请日：2004-05-26
申请人： Yoshiharu Kato , Gen Tsukishiro , Yoshihiro Takemae
发明人： Yoshiharu Kato , Gen Tsukishiro , Yoshihiro Takemae
IPC分类号： G06F12/00 , G06F12/02 , G06F13/42 , G11C8/00 , G11C11/406
CPC分类号： G06F13/4243 , G11C11/406 , Y02D10/14 , Y02D10/151
摘要： It is intended to provide a memory control device and memory control method capable of reducing charge/discharge current consumed while various commands are inputted to a semiconductor memory device and reducing occurrence of power noises. During periods TT1, TT2, and TT3 which are parts of a period tCKE in which a clock enable signal CKE is in active state, supply of a control clock SD_CLK from a memory control device 1 to a synchronous-type semiconductor memory device 12 can be stopped. Furthermore, in case an input of a data input/output period of an external command and that of refresh operation period of a refresh command RCMD overlap and an access region of the external command and that of the refresh command RCMD do not coincide, those commands are converted to control command signal SD_CMD in parallel, whereby parallel conversion processing operation can be conducted.
摘要翻译：旨在提供一种存储器控制装置和存储器控制方法，其能够在将各种命令输入到半导体存储器件中时减少所消耗的充电/放电电流并减少电力噪声的发生。在时钟使能信号CKE处于活动状态的周期tCKE的一部分的时段TT 1，TT 2和TT 3期间，将控制时钟SD_CLK从存储器控制装置1提供给同步型半导体存储器件 12可以停止。此外，在外部命令的数据输入/输出周期的输入和刷新命令RCMD的刷新操作周期的输入与外部命令的访问区域和刷新命令RCMD的访问区域不重合的情况下，这些命令被并行地转换为控制指令信号SD_CMD，由此可以进行并行转换处理操作。

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