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1. 发明授权

US07042798B2 Memory control device and memory control method 有权
标题翻译：内存控制装置和内存控制方式
公开(公告)号：US07042798B2
公开(公告)日：2006-05-09
申请号：US10853313
申请日：2004-05-26
申请人： Yoshiharu Kato , Gen Tsukishiro , Yoshihiro Takemae
发明人： Yoshiharu Kato , Gen Tsukishiro , Yoshihiro Takemae
IPC分类号： G11C8/00
CPC分类号： G06F13/4243 , G11C11/406 , Y02D10/14 , Y02D10/151
摘要： It is intended to provide a memory control device and memory control method capable of reducing charge/discharge current consumed while various commands are inputted to a semiconductor memory device and reducing occurrence of power noises. During periods TT1, TT2, and TT3 which are parts of a period tCKE in which a clock enable signal CKE is in active state, supply of a control clock SD_CLK from a memory control device 1 to a synchronous-type semiconductor memory device 12 can be stopped. Furthermore, in case an input of a data input/output period of an external command and that of refresh operation period of a refresh command RCMD overlap and an access region of the external command and that of the refresh command RCMD do not coincide, those commands are converted to control command signal SD_CMD in parallel, whereby parallel conversion processing operation can be conducted.
摘要翻译：旨在提供一种存储器控制装置和存储器控制方法，其能够在将各种命令输入到半导体存储器件中时减少所消耗的充电/放电电流并减少电力噪声的发生。在时钟使能信号CKE处于活动状态的周期tCKE的一部分的时段TT 1，TT 2和TT 3期间，将控制时钟SD_CLK从存储器控制装置1提供给同步型半导体存储器件 12可以停止。此外，在外部命令的数据输入/输出周期的输入和刷新命令RCMD的刷新操作周期的输入与外部命令的访问区域和刷新命令RCMD的访问区域不重合的情况下，这些命令被并行地转换为控制指令信号SD_CMD，由此可以进行并行转换处理操作。

2. 发明申请

US20050157585A1 Memory control device and memory control method 有权
标题翻译：内存控制装置和内存控制方式
公开(公告)号：US20050157585A1
公开(公告)日：2005-07-21
申请号：US10853313
申请日：2004-05-26
申请人： Yoshiharu Kato , Gen Tsukishiro , Yoshihiro Takemae
发明人： Yoshiharu Kato , Gen Tsukishiro , Yoshihiro Takemae
IPC分类号： G06F12/00 , G06F12/02 , G06F13/42 , G11C8/00 , G11C11/406
CPC分类号： G06F13/4243 , G11C11/406 , Y02D10/14 , Y02D10/151
摘要： It is intended to provide a memory control device and memory control method capable of reducing charge/discharge current consumed while various commands are inputted to a semiconductor memory device and reducing occurrence of power noises. During periods TT1, TT2, and TT3 which are parts of a period tCKE in which a clock enable signal CKE is in active state, supply of a control clock SD_CLK from a memory control device 1 to a synchronous-type semiconductor memory device 12 can be stopped. Furthermore, in case an input of a data input/output period of an external command and that of refresh operation period of a refresh command RCMD overlap and an access region of the external command and that of the refresh command RCMD do not coincide, those commands are converted to control command signal SD_CMD in parallel, whereby parallel conversion processing operation can be conducted.
摘要翻译：旨在提供一种存储器控制装置和存储器控制方法，其能够在将各种命令输入到半导体存储器件中时减少所消耗的充电/放电电流并减少电力噪声的发生。在时钟使能信号CKE处于活动状态的周期tCKE的一部分的时段TT 1，TT 2和TT 3期间，将控制时钟SD_CLK从存储器控制装置1提供给同步型半导体存储器件 12可以停止。此外，在外部命令的数据输入/输出周期的输入和刷新命令RCMD的刷新操作周期的输入与外部命令的访问区域和刷新命令RCMD的访问区域不重合的情况下，这些命令被并行地转换为控制指令信号SD_CMD，由此可以进行并行转换处理操作。

3. 发明申请

US20070091678A1 Memory system and operating method of same 有权
标题翻译：内存系统和操作方法相同
公开(公告)号：US20070091678A1
公开(公告)日：2007-04-26
申请号：US11583129
申请日：2006-10-19
申请人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
发明人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
IPC分类号： G11C16/06
CPC分类号： G11C16/32 , G06F11/1068 , G11C7/1006 , G11C2029/0411 , G11C2207/104
摘要： A volatile memory has a volatile additional area for storing an error correction code for a nonvolatile memory. Data stored in the nonvolatile memory are transferred to the volatile memory together with the error correction code without making an error correction. Thus, data transfer time from the nonvolatile memory to the volatile memory can be shortened. As a result, it is possible to shorten the time from beginning of the data transfer from the nonvolatile memory to the volatile memory to a point at which data becomes accessible.
摘要翻译：易失性存储器具有用于存储用于非易失性存储器的纠错码的易失性附加区域。存储在非易失性存储器中的数据与错误校正码一起传送到易失性存储器，而不进行纠错。因此，可以缩短从非易失性存储器到易失性存储器的数据传送时间。结果，可以缩短从非易失性存储器到易失性存储器的数据传输开始到数据可访问的时间。

4. 发明申请

US20070091989A1 Signal interface 有权
标题翻译：信号接口
公开(公告)号：US20070091989A1
公开(公告)日：2007-04-26
申请号：US11583130
申请日：2006-10-19
申请人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
发明人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
IPC分类号： H04L5/16 , H04L25/00
CPC分类号： H04L25/0282 , H04L5/04 , H04L25/0294
摘要： Plural transmitter units generate plural currents corresponding to plural logical values, respectively, and propagate the currents to a common signal line. The common signal line synthesizes the currents generated by the transmitter units, and propagates them to a receiver unit as a synthetic current. The receiver unit restores the logical values the transmitter units generated, in accordance with the synthetic current. The values of the currents the transmitter units generate in correspondence with the logical values each differ, so that the value of the synthetic current can be changed for every combination of logical values. Accordingly, the receiver unit can restore the logical values outputted from the respective transmitter units, based on the synthetic current. That is, employing the common signal line enables signals transmitted from the transmitter units to be simultaneously received. Consequently, the number of signal lines laid between the transmitter units and the receiver unit is reduced.
摘要翻译：多个发射机单元分别产生对应于多个逻辑值的多个电流，并将电流传播到公共信号线。公共信号线合成由发射机单元产生的电流，并将其作为合成电流传播到接收机单元。接收器单元根据合成电流恢复发射机单元产生的逻辑值。发射机单元对应于逻辑值产生的电流值各自不同，使得可以针对逻辑值的每个组合来改变合成电流的值。因此，接收机单元可以基于合成电流来恢复从各个发射机单元输出的逻辑值。也就是说，采用公共信号线使得能够同时接收从发送单元发送的信号。因此，放置在发射机单元和接收机单元之间的信号线的数量减少。

5. 发明授权

US07827468B2 Memory system including nonvolatile memory and volatile memory and operating method of same 有权
标题翻译：存储系统包括非易失性存储器和易失性存储器及其操作方法
公开(公告)号：US07827468B2
公开(公告)日：2010-11-02
申请号：US11583129
申请日：2006-10-19
申请人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
发明人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
IPC分类号： G11C29/00
CPC分类号： G11C16/32 , G06F11/1068 , G11C7/1006 , G11C2029/0411 , G11C2207/104
摘要： A volatile memory has a volatile additional area for storing an error correction code for a nonvolatile memory. Data stored in the nonvolatile memory are transferred to the volatile memory together with the error correction code without making an error correction. Thus, data transfer time from the nonvolatile memory to the volatile memory can be shortened. As a result, it is possible to shorten the time from beginning of the data transfer from the nonvolatile memory to the volatile memory to a point at which data becomes accessible.
摘要翻译：易失性存储器具有用于存储用于非易失性存储器的纠错码的易失性附加区域。存储在非易失性存储器中的数据与错误校正码一起传送到易失性存储器，而不进行纠错。因此，可以缩短从非易失性存储器到易失性存储器的数据传送时间。结果，可以缩短从非易失性存储器到易失性存储器的数据传输开始到数据可访问的时间。

6. 发明授权

US07388791B2 Signal interface 有权
标题翻译：信号接口
公开(公告)号：US07388791B2
公开(公告)日：2008-06-17
申请号：US11583130
申请日：2006-10-19
申请人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
发明人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
IPC分类号： G11C7/10
CPC分类号： H04L25/0282 , H04L5/04 , H04L25/0294
摘要： Plural transmitter units generate plural currents corresponding to plural logical values, respectively, and propagate the currents to a common signal line. The common signal line synthesizes the currents generated by the transmitter units, and propagates them to a receiver unit as a synthetic current. The receiver unit restores the logical values the transmitter units generated, in accordance with the synthetic current. The values of the currents the transmitter units generate in correspondence with the logical values each differ, so that the value of the synthetic current can be changed for every combination of logical values. Accordingly, the receiver unit can restore the logical values outputted from the respective transmitter units, based on the synthetic current. That is, employing the common signal line enables signals transmitted from the transmitter units to be simultaneously received. Consequently, the number of signal lines laid between the transmitter units and the receiver unit is reduced.
摘要翻译：多个发射机单元分别产生对应于多个逻辑值的多个电流，并将电流传播到公共信号线。公共信号线合成由发射机单元产生的电流，并将其作为合成电流传播到接收机单元。接收器单元根据合成电流恢复发射机单元产生的逻辑值。发射机单元对应于逻辑值产生的电流值各自不同，使得可以针对逻辑值的每个组合来改变合成电流的值。因此，接收机单元可以基于合成电流来恢复从各个发射机单元输出的逻辑值。也就是说，采用公共信号线使得能够同时接收从发送单元发送的信号。因此，放置在发射机单元和接收机单元之间的信号线的数量减少。

7. 发明授权

US5499213A Semiconductor memory device having self-refresh function 失效
标题翻译：具有自刷新功能的半导体存储器件
公开(公告)号：US5499213A
公开(公告)日：1996-03-12
申请号：US83443
申请日：1993-06-29
申请人： Makoto Niimi , Shigemasa Ito , Toyonobu Yamada , Yoshihiro Takemae , Yoshiharu Kato
发明人： Makoto Niimi , Shigemasa Ito , Toyonobu Yamada , Yoshihiro Takemae , Yoshiharu Kato
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A semiconductor memory device has an oscillator unit for generating refresh pulses, a refresh address detection unit for detecting refreshed addresses and outputting a predetermined signal upon the completion of the refreshing of all addresses, and an output control unit for continuing a self-refresh mode to refresh all addresses according to the signal from the refresh address detection unit, before releasing the self-refresh mode in response to an external signal. Therefore, the refresh operation is continued until all cells are refreshed, thereby data stored in the semiconductor memory device is not lost and is correctly refreshed.
摘要翻译：半导体存储器件具有用于产生刷新脉冲的振荡器单元，刷新地址检测单元，用于检测刷新的地址并在完成所有地址的刷新时输出预定信号;以及输出控制单元，用于继续自刷新模式在响应于外部信号释放自刷新模式之前，根据刷新地址检测单元的信号刷新所有地址。因此，继续刷新操作直到所有单元被刷新，从而存储在半导体存储器件中的数据不会丢失并被正确地刷新。

8. 发明授权

US08886897B2 Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips 有权
公开(公告)号：US08886897B2
公开(公告)日：2014-11-11
申请号：US11505835
申请日：2006-08-18
申请人： Yoshihiro Takemae
发明人： Yoshihiro Takemae
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F13/16 , G06F12/02 , G06F12/06 , G11C5/04
CPC分类号： G06F3/0626 , G06F3/0658 , G06F3/0659 , G06F3/068 , G06F3/0688 , G06F12/00 , G06F12/0246 , G06F12/0623 , G06F13/1694 , G06F2212/7201 , G11C5/04 , G11C7/1072
摘要： A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

9. 发明授权

US08766711B2 Switching circuit with controlled driver circuit 有权
标题翻译：具有受控驱动电路的开关电路
公开(公告)号：US08766711B2
公开(公告)日：2014-07-01
申请号：US13345112
申请日：2012-01-06
申请人： Yoshihiro Takemae
发明人： Yoshihiro Takemae
IPC分类号： H03K3/01
CPC分类号： H02M3/155 , H03K17/6877
摘要： A switching circuit device has a first transistor which has a drain coupled to a high-potential terminal, a source coupled to a low-potential power supply, and, a driving circuit, which outputs, to a gate of the first transistor in response to an input control signal, a pulse having a potential higher than a threshold voltage of the first transistor and a potential of the low-potential power supply, wherein the driving circuit has a first inverter including a second transistor provided between the gate and the source of the first transistor, wherein when the first transistor changes from on to off due to the pulse, the second transistor conducts and short-circuits the gate and the source of the first transistor.
摘要翻译：开关电路器件具有第一晶体管，其具有耦合到高电位端子的漏极，耦合到低电位电源的源极和驱动电路，其响应于第一晶体管输出到第一晶体管的栅极输入控制信号，具有高于第一晶体管的阈值电压的电位的脉冲和低电位电源的电位，其中驱动电路具有第一反相器，该第一反相器包括设置在栅极和源极之间的第二晶体管第一晶体管，其中当第一晶体管由于脉冲而从接通变为截止时，第二晶体管导通并使第一晶体管的栅极和源极短路。

10. 发明申请

US20120091986A1 SEMICONDUCTOR DEVICE AND POWER SUPPLY APPARATUS 审中-公开
标题翻译：半导体器件和电源设备
公开(公告)号：US20120091986A1
公开(公告)日：2012-04-19
申请号：US13181710
申请日：2011-07-13
申请人： Yoshihiro Takemae , Tsutomu Hosoda
发明人： Yoshihiro Takemae , Tsutomu Hosoda
IPC分类号： G05F3/08 , H01L27/088
CPC分类号： H01L27/088 , G05F3/08 , H01L21/8252 , H01L27/0605
摘要： A semiconductor device includes a first transistor including a GaN-based semiconductor stacked structure formed over a substrate, a first gate electrode having a plurality of first fingers over the semiconductor stacked structure, a plurality of first drain electrodes provided along the first fingers, and a plurality of first source electrodes provided along the first fingers; a second transistor including the semiconductor stacked structure, a second gate electrode having a plurality of second fingers over the semiconductor stacked structure, the second drain electrodes provided along the second fingers, and a plurality of second source electrodes provided along the second fingers; a drain pad provided over or under the first drain electrodes, and coupled to the first drain electrodes; a source pad provided over or under the second source electrodes, and coupled to the second source electrodes; and a common pad coupled to the first source electrodes and the second drain electrodes.
摘要翻译：半导体器件包括：第一晶体管，包括在衬底上形成的GaN基半导体层叠结构，在半导体层叠结构上具有多个第一指状物的第一栅电极，沿着第一指状物设置的多个第一漏电极，沿着第一指状物设置的多个第一源电极; 包括半导体层叠结构的第二晶体管，在半导体堆叠结构上具有多个第二指状物的第二栅极电极，沿着第二指状物设置的第二漏极电极以及沿着第二指状物设置的多个第二源极电极; 漏极焊盘，设置在所述第一漏电极之上或之下，并且耦合到所述第一漏电极; 源极焊盘，设置在所述第二源电极之上或之下，并且耦合到所述第二源电极; 以及耦合到第一源极和第二漏极的公共焊盘。

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