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1. 发明授权

US08982650B2 Memory interface circuit and timing adjusting method 有权
标题翻译：存储器接口电路和时序调整方法
公开(公告)号：US08982650B2
公开(公告)日：2015-03-17
申请号：US13612771
申请日：2012-09-12
申请人： Hitoaki Nishiwaki , Shinichiro Ikeda
发明人： Hitoaki Nishiwaki , Shinichiro Ikeda
IPC分类号： G11C7/00 , G11C7/10 , G11C11/4076 , G11C11/4096
CPC分类号： G11C7/00 , G11C7/1066 , G11C7/1072 , G11C11/4076 , G11C11/4096
摘要： A memory interface circuit, which controls capture timing of data provided from a memory according to a strobe signal provided from the memory, includes a control unit that controls an activation timing of an internal strobe gate signal, which masks the strobe signal when being deactivated, by delaying the internal strobe gate signal by a first period shorter than one cycle time of a clock signal to generate an internal strobe gate adjustment signal, and by adjusting an activation timing of the adjustment signal. A detection unit outputs a detection signal, when the strobe signal changes from a first potential to a second potential higher than the first potential, or when the first potential of the strobe signal continues for a second period or longer. The control unit adjusts the activation timing of the adjustment signal in accordance with the detection signal.
摘要翻译：一种存储器接口电路，其根据从存储器提供的选通信号来控制从存储器提供的数据的捕获定时，包括控制单元，其控制内部选通门信号的激活定时，其在去激活时屏蔽选通信号，通过将内部选通栅极信号延迟比时钟信号的一个周期时间短的第一周期，以产生内部选通栅极调整信号，并通过调整调整信号的激活定时。当选通信号从第一电位变为高于第一电位的第二电位时，或者当选通信号的第一电位持续第二期间或更长时，检测单元输出检测信号。控制单元根据检测信号调整调整信号的激活定时。

2. 发明申请

US20130070544A1 MEMORY INTERFACE CIRCUIT AND TIMING ADJUSTING METHOD 有权
标题翻译：存储器接口电路和时序调整方法
公开(公告)号：US20130070544A1
公开(公告)日：2013-03-21
申请号：US13612771
申请日：2012-09-12
申请人： Hitoaki NISHIWAKI , Shinichiro Ikeda
发明人： Hitoaki NISHIWAKI , Shinichiro Ikeda
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/1066 , G11C7/1072 , G11C11/4076 , G11C11/4096
摘要： A memory interface circuit, which controls capture timing of data provided from a memory according to a strobe signal provided from the memory, includes a control unit that controls an activation timing of an internal strobe gate signal, which masks the strobe signal when being deactivated, by delaying the internal strobe gate signal by a first period shorter than one cycle time of a clock signal to generate an internal strobe gate adjustment signal, and by adjusting an activation timing of the adjustment signal. A detection unit outputs a detection signal, when the strobe signal changes from a first potential to a second potential higher than the first potential, or when the first potential of the strobe signal continues for a second period or longer. The control unit adjusts the activation timing of the adjustment signal in accordance with the detection signal.
摘要翻译：一种存储器接口电路，其根据从存储器提供的选通信号来控制从存储器提供的数据的捕获定时，包括控制单元，其控制内部选通门信号的激活定时，其在去激活时屏蔽选通信号，通过将内部选通栅极信号延迟比时钟信号的一个周期时间短的第一周期，以产生内部选通栅极调整信号，并通过调整调整信号的激活定时。当选通信号从第一电位变为高于第一电位的第二电位时，或者当选通信号的第一电位持续第二期间或更长时，检测单元输出检测信号。控制单元根据检测信号调整调整信号的激活定时。

3. 发明授权

US06385127B1 Synchronous semiconductor device and method for latching input signals 有权
标题翻译：用于锁存输入信号的同步半导体器件和方法
公开(公告)号：US06385127B1
公开(公告)日：2002-05-07
申请号：US09832851
申请日：2001-04-12
申请人： Shinichiro Ikeda
发明人： Shinichiro Ikeda
IPC分类号： G11C800
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1087 , G11C8/06 , G11C8/18
摘要： A compact synchronous semiconductor device having an improved set-up/hold time is disclosed. A decoder receives input signals and generates decoded signals. A delay-adjusting unit adjusts the delay time of each of the decoded signals and provides adjusted decoded signals. A latch circuit unit latches the adjusted decoded signals in synchronism with a clock signal.
摘要翻译：公开了一种具有改进的设置/保持时间的紧凑型同步半导体器件。解码器接收输入信号并产生解码信号。延迟调整单元调整每个解码信号的延迟时间并提供经调整的解码信号。锁存电路单元与时钟信号同步地锁存经调整的解码信号。

4. 发明授权

US08185760B2 Memory controller device, control method for memory controller device and data reception device 有权
标题翻译：存储控制器设备，存储控制器设备和数据接收设备的控制方法
公开(公告)号：US08185760B2
公开(公告)日：2012-05-22
申请号：US12411085
申请日：2009-03-25
申请人： Akihiro Takakura , Shinichiro Ikeda
发明人： Akihiro Takakura , Shinichiro Ikeda
IPC分类号： G06F1/32
CPC分类号： G06F1/08 , G06F13/1689
摘要： A memory controller device coupled to a memory device equipment including a plurality of memory devices, includes a memory controller configured to instruct read-out of data in the memory device and a physical part configured to terminate a read-out signal for a certain period containing an arrival time of data read out from one memory device of the memory device equipment in accordance with a read-out instruction from the memory controller and excludes a part of a delay time from the read-out instruction until the data read-out of at least one other memory device.
摘要翻译：一种连接到包括多个存储器件的存储器件设备的存储器控制器设备，包括：存储器控制器，被配置为指示读出存储器件中的数据;以及物理部件，被配置为在一段时间内终止读出信号，根据来自存储器控制器的读出指令从存储器件设备的一个存储器件读出数据的到达时间，并且从读出指令中排除延迟时间的一部分，直到数据读出至少一个其他存储设备。

5. 发明授权

US07859284B2 Semiconductor device and semiconductor device module 有权
标题翻译：半导体器件和半导体器件模块
公开(公告)号：US07859284B2
公开(公告)日：2010-12-28
申请号：US12058241
申请日：2008-03-28
申请人： Shinichiro Ikeda
发明人： Shinichiro Ikeda
IPC分类号： G01R31/02
CPC分类号： G01R31/31712 , G01R31/31723 , G01R31/318513 , H01L25/18 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L2924/13091 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： To provide a semiconductor module and a semiconductor device enabling more accurate testing of the connection state of the internal wiring between the semiconductor devices. The semiconductor device has switches SW11 through SW13 that connect a test terminal TT to one end side of wires to be tested, and transistors M21 through M23 that supply a ground potential VSS to the other end side of the wires to be tested. When a power source potential VDD is supplied to one end of the wires to be tested and a ground potential VSS is supplied to the other end of the wires to be tested, a current path can be formed including the wires to be tested. If a power source potential VDD is supplied to the wires to be tested and a ground potential VSS is supplied to the wires which are not to be tested, a difference in potential can be generated between the wires to be tested and the rest of the wires, which makes it possible to detect a short circuit failure.
摘要翻译：提供一种能够更准确地测试半导体器件之间的内部布线的连接状态的半导体模块和半导体器件。半导体器件具有将测试端子TT连接到要测试的导线的一端侧的开关SW11至SW13以及将待接地的电线的另一端侧提供接地电位VSS的晶体管M21至M23。当将电源电位VDD提供给要测试的导线的一端并且接地电位VSS被提供给待测试的导线的另一端时，可以形成包括待测试的导线的电流路径。如果将电源电位VDD提供给要测试的导线，并且将接地电位VSS提供给不被测试的导线，则可以在待测试的导线与其余线之间产生电位差，这使得可以检测短路故障。

6. 发明申请

US20090249110A1 MEMORY CONTROLLER DEVICE, CONTROL METHOD FOR MEMORY CONTROLLER DEVICE AND DATA RECEPTION DEVICE 有权
标题翻译：存储器控制器装置，用于存储器控制器装置和数据接收装置的控制方法
公开(公告)号：US20090249110A1
公开(公告)日：2009-10-01
申请号：US12411085
申请日：2009-03-25
申请人： Akihiro TAKAKURA , Shinichiro Ikeda
发明人： Akihiro TAKAKURA , Shinichiro Ikeda
IPC分类号： G06F1/08 , G06F12/00
CPC分类号： G06F1/08 , G06F13/1689
摘要： A memory controller device coupled to a memory device equipment including a plurality of memory devices, includes a memory controller configured to instruct read-out of data in the memory device and a physical part configured to terminate a read-out signal for a certain period containing an arrival time of data read out from one memory device of the memory device equipment in accordance with a read-out instruction from the memory controller and excludes a part of a delay time from the read-out instruction until the data read-out of at least one other memory device.
摘要翻译：一种连接到包括多个存储器件的存储器件设备的存储器控制器设备，包括：存储器控制器，被配置为指示读出存储器件中的数据;以及物理部件，被配置为在一段时间内终止读出信号，根据来自存储器控制器的读出指令从存储器件设备的一个存储器件读出数据的到达时间，并且从读出指令中排除延迟时间的一部分，直到数据读出至少一个其他存储设备。

7. 发明授权

US06466492B2 Synchronous semiconductor memory device and method for controlling mask data input circuit 失效
标题翻译：同步半导体存储器件和控制掩模数据输入电路的方法
公开(公告)号：US06466492B2
公开(公告)日：2002-10-15
申请号：US09941765
申请日：2001-08-30
申请人： Shinichiro Ikeda
发明人： Shinichiro Ikeda
IPC分类号： G11C710
CPC分类号： G11C7/1093 , G11C7/1006 , G11C7/1015 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C11/4076 , G11C11/4093
摘要： A method for controlling an input circuit of a synchronous semiconductor memory device that reduces current consumption without changing commands or increasing signal input terminals. The synchronous semiconductor memory device includes an input circuit for receiving write data and is operated based on a synchronizing signal. When the synchronous semiconductor memory device is active, the input circuit is selectively inactivated based on a mask control signal, which masks the write data. When the synchronous semiconductor memory device enters a write mode in which the synchronous semiconductor memory device stores data, the input circuit is activated and the mask control signal is invalidated.
摘要翻译：一种用于控制同步半导体存储器件的输入电路的方法，其在不改变命令或增加信号输入端子的情况下降低电流消耗。同步半导体存储器件包括用于接收写入数据的输入电路，并且基于同步信号进行操作。当同步半导体存储器件有效时，基于屏蔽该写入数据的掩码控制信号选择性地使输入电路失效。当同步半导体存储器件进入同步半导体存储器件存储数据的写入模式时，输入电路被激活，掩模控制信号无效。

8. 发明授权

US06411564B1 Semiconductor memory device and synchronous memory 有权
公开(公告)号：US06411564B1
公开(公告)日：2002-06-25
申请号：US09855656
申请日：2001-05-16
申请人： Shinichiro Ikeda
发明人： Shinichiro Ikeda
IPC分类号： G11C700
摘要： The present invention provides a semiconductor memory device for storing data. The semiconductor memory device performs data masking without increasing power consumption regardless of latency. The device includes a data output circuit for receiving and outputting the stored data. A mask signal input circuit receives a mask signal used to mask the data output from the data output circuit and provides the mask signal to the data output circuit. An input control circuit generates an activation signal that activates the mask signal input circuit and provides the activation signal to the mask signal input circuit. The input control circuit generates the activation signal based on a mode setting signal and a latency determination signal. The mode setting signal is used to activate the mask signal input circuit and set an operation mode of the semiconductor memory device. The latency determination signal has a level corresponding to latency information.

9. 发明申请

US20080205170A1 DDR-SDRAM INTERFACE CIRCUITRY, AND METHOD AND SYSTEM FOR TESTING THE INTERFACE CIRCUITRY 审中-公开
标题翻译： DDR-SDRAM接口电路，以及用于测试接口电路的方法和系统
公开(公告)号：US20080205170A1
公开(公告)日：2008-08-28
申请号：US12039316
申请日：2008-02-28
申请人： Shinichiro IKEDA
发明人： Shinichiro IKEDA
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028
摘要： According to one aspect of an embodiment of the present invention, there is provided a memory interface circuit including a first data output circuit which outputs a data signal based on a data strobe signal, the memory interface circuit comprising: a first delay-locked loop circuit that adjusts a delay of the data strobe signal and outputs the data strobe signal at a first timing; and a second data output circuit that outputs the data signal at a second timing different from the first timing during a normal operation, and outputs the data signal at the first timing during a test operation.
摘要翻译：根据本发明的实施例的一个方面，提供了一种存储器接口电路，包括：第一数据输出电路，其基于数据选通信号输出数据信号;所述存储器接口电路包括：第一延迟锁定环路调整数据选通信号的延迟并在第一定时输出数据选通信号; 以及第二数据输出电路，其在正常操作期间以与第一定时不同的第二定时输出数据信号，并且在测试操作期间以第一定时输出数据信号。

10. 发明授权

US07133996B2 Memory device and internal control method therefor 有权
公开(公告)号：US07133996B2
公开(公告)日：2006-11-07
申请号：US10279963
申请日：2002-10-25
申请人： Shinichiro Ikeda , Yoshiharu Kato
发明人： Shinichiro Ikeda , Yoshiharu Kato
IPC分类号： G06F12/06
CPC分类号： G11C11/4076 , G11C11/4074 , G11C11/4087
摘要： A memory device for ensuring efficient access and reduction in current consumption. The memory device includes a plurality of memory cells arranged in accordance with a first address and a second address which define a logical address map indicating a logical shape of the memory array. An address map changing unit is operatively coupled to the memory array, for receiving a first address signal for generating the first address and a second address signal for generating the second address. The address map changing unit is capable of changing the logical address map by altering a part of one of the first address signal and the second address signal.

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