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1. 发明授权

US5217917A Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor 失效
标题翻译：具有改进的基板布置以允许形成多种不同类型的随机存取存储器的半导体存储器件及其测试方法
公开(公告)号：US5217917A
公开(公告)日：1993-06-08
申请号：US496280
申请日：1990-03-20
申请人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takemuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
发明人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takemuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
IPC分类号： G11C5/00 , G11C5/02 , G11C7/10 , G11C11/4074 , G11C11/408 , G11C11/4096 , G11C29/00 , G11C29/02 , G11C29/46 , G11C29/50
CPC分类号： G11C29/027 , G11C11/4074 , G11C11/4082 , G11C11/4096 , G11C29/02 , G11C29/46 , G11C29/50 , G11C29/50012 , G11C5/00 , G11C5/025 , G11C7/1045 , G11C11/401 , G11C2029/5006 , G11C29/78
摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.
摘要翻译：提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。结合这些，接合垫被布置在适于不同包装类型的最佳位置处。还提供了各种布局布置以最小化空间并改善访问时间。提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

2. 发明授权

US5426613A Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor 失效
标题翻译：具有改进的基板布置以允许形成多种不同类型的随机存取存储器的半导体存储器件及其测试方法
公开(公告)号：US5426613A
公开(公告)日：1995-06-20
申请号：US972907
申请日：1992-11-06
申请人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
发明人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
IPC分类号： G11C5/00 , G11C5/02 , G11C7/10 , G11C11/4074 , G11C11/408 , G11C11/4096 , G11C29/00 , G11C29/02 , G11C29/46 , G11C29/50 , G11C7/00 , G11C8/00
CPC分类号： G11C29/027 , G11C11/4074 , G11C11/4082 , G11C11/4096 , G11C29/02 , G11C29/46 , G11C29/50 , G11C29/50012 , G11C5/00 , G11C5/025 , G11C7/1045 , G11C11/401 , G11C2029/5006 , G11C29/78
摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.
摘要翻译：提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。结合这些，接合垫被布置在适于不同包装类型的最佳位置处。还提供了各种布局布置以最小化空间并改善访问时间。提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

3. 发明授权

US5805513A Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor 失效
公开(公告)号：US5805513A
公开(公告)日：1998-09-08
申请号：US432867
申请日：1995-05-02
申请人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
发明人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
IPC分类号： G11C5/00 , G11C5/02 , G11C7/10 , G11C11/4074 , G11C11/408 , G11C11/4096 , G11C29/00 , G11C29/02 , G11C29/46 , G11C29/50 , G11C7/00
CPC分类号： G11C29/027 , G11C11/4074 , G11C11/4082 , G11C11/4096 , G11C29/02 , G11C29/46 , G11C29/50 , G11C29/50012 , G11C5/00 , G11C5/025 , G11C7/1045 , G11C11/401 , G11C2029/5006 , G11C29/78
摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

4. 发明授权

US5598373A Semiconductor memory system 失效
标题翻译：半导体存储器系统
公开(公告)号：US5598373A
公开(公告)日：1997-01-28
申请号：US476765
申请日：1995-06-07
申请人： Shoji Wada , Kanehide Kenmizaki , Masaya Muranaka , Masahiro Ogata , Hidetomo Aoyagi , Tetsuya Kitame , Masahiro Katayama , Shoji Kubono , Yukihide Suzuki , Makoto Morino , Sinichi Miyatake , Seiichi Shundo , Yoshihisa Koyama , Nobuhiko Ohno
发明人： Shoji Wada , Kanehide Kenmizaki , Masaya Muranaka , Masahiro Ogata , Hidetomo Aoyagi , Tetsuya Kitame , Masahiro Katayama , Shoji Kubono , Yukihide Suzuki , Makoto Morino , Sinichi Miyatake , Seiichi Shundo , Yoshihisa Koyama , Nobuhiko Ohno
IPC分类号： G06F12/16 , G11C29/00 , G11C29/02 , G11C29/44 , H01L21/82 , G11C7/00 , G11C8/00 , G11C11/34
CPC分类号： G11C29/80 , G11C29/02 , G11C29/44
摘要： A defect remedy LSI mounted on a memory module, comprising: an input interface portion for capturing address and control signals, the input interface portion being the same as that of a dynamic RAM; an input/output interface portion corresponding to a data bus of a memory device comprised of a plurality of dynamic random access memories; a memory circuit to which a chip address and an X defective address of any of the plurality of random access memories are electrically written, the memory circuit being substantially made nonvolatile; a redundancy remedy RAM portion composed of a static RAM wherein a word line is selected by a compare match signal between an X address signal and the defective address of the memory circuit, the X address signal and the defective address being captured via the input interface portion, and a column is selected by a Y address signal captured via the input interface portion; a selecting portion for connecting a data input/output bus of the redundancy remedy RAM portion to an input/output circuit corresponding to a defective chip address; a data input/output portion for selectively activating an input/output circuit to be connected to a data bus corresponding to a dynamic RAM found defective; and a mask portion for outputting a control signal for putting in a high-impedance state an output pin of the defective RAM in a read operation.
摘要翻译：安装在存储器模块上的缺陷补救LSI包括：用于捕获地址和控制信号的输入接口部分，所述输入接口部分与动态RAM的相同; 对应于由多个动态随机存取存储器构成的存储器件的数据总线的输入/输出接口部分; 存储器电路，其中电子地写入多个随机存取存储器中的任何一个的芯片地址和X缺陷地址，所述存储器电路基本上是非易失性的; 由静态RAM组成的冗余补救RAM部分，其中通过X地址信号和存储器电路的缺陷地址之间的比较匹配信号来选择字线，X地址信号和缺陷地址经由输入接口部分捕获并且通过经由输入接口部分捕获的Y地址信号来选择列; 选择部分，用于将冗余补救RAM部分的数据输入/输出总线连接到对应于有缺陷的芯片地址的输入/输出电路; 数据输入/输出部分，用于选择性地激活要连接到与发现有缺陷的动态RAM相对应的数据总线的输入/输出电路; 以及掩模部分，用于在读取操作中输出用于将缺陷RAM的输出引脚置于高阻抗状态的控制信号。

5. 发明授权

US5440521A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5440521A
公开(公告)日：1995-08-08
申请号：US109071
申请日：1993-08-19
申请人： Manabu Tsunozaki , Kyoko Ishii , Koichi Nozaki , Hiroshi Yoshioka , Yoshihisa Koyama , Shinji Udo , Hidetomo Aoyagi , Sinichi Miyatake , Makoto Morino , Akihiko Hoshida
发明人： Manabu Tsunozaki , Kyoko Ishii , Koichi Nozaki , Hiroshi Yoshioka , Yoshihisa Koyama , Shinji Udo , Hidetomo Aoyagi , Sinichi Miyatake , Makoto Morino , Akihiko Hoshida
IPC分类号： G11C11/401 , G11C5/02 , H01L27/108 , H01L27/10
CPC分类号： H01L27/10805 , G11C5/025
摘要： A semiconductor integrated circuit device constituted by a plurality of sets each of which having a pair of memory mats and each memory mat having a plurality of memory cells arranged in a matrix and a sense amplifier, I/O lines for transmitting signals provided by the sense amplifiers, selecting circuitry for selecting either a condition for sending out the signals provided by the sense amplifiers on the I/O lines or a condition for not sending out the same on the I/O lines, and Y-selection lines for transmitting the selection signals. A decoder connected with selection is disposed substantially at the middle of the Y-selection lines. X- and Y-address buffers are disposed close to each other nearer to the center of the chip than X- and Y-redundant circuits. A reference voltage generating circuit is disposed nearer to the edge of the chip than an output buffer circuit. A relief selecting circuit of each memory mat is formed adjacent to a redundant line selecting circuits included in the same memory mat. At least some of wiring lines connected to each sense amplifier are formed in a wiring layer in which Y-selection lines are formed. The Y-selection lines are extended in gaps between the sense amplifiers.
摘要翻译：一种半导体集成电路器件，由多个组合构成，每组具有一对存储器阵列，每个存储器阵列具有以矩阵形式排列的多个存储单元，以及一个读出放大器，用于发送由该感测器提供的信号的I / O线放大器，用于选择用于发送由I / O线上的读出放大器提供的信号的条件的选择电路或用于在I / O线上不发送其的条件，以及用于发送选择的Y选择线信号。连接有选择的解码器基本上设置在Y选择线的中间。 X和Y地址缓冲器被布置成比X和Y冗余电路更靠近芯片的中心。参考电压产生电路设置成比输出缓冲电路更靠近芯片的边缘。每个存储器垫的浮雕选择电路与包括在同一存储器垫中的冗余线选择电路相邻地形成。连接到每个读出放大器的至少一些布线形成在其中形成Y选择线的布线层中。 Y选择线在读出放大器之间的间隙中扩展。

6. 发明授权

US06897496B2 Semiconductor device, a method of manufacturing the same and storage media 有权
标题翻译：半导体器件，其制造方法和存储介质
公开(公告)号：US06897496B2
公开(公告)日：2005-05-24
申请号：US09982839
申请日：2001-10-22
申请人： Toshio Yamada , Kazumasa Yanagisawa , Yoshihiro Shinozaki , Hidetomo Aoyagi
发明人： Toshio Yamada , Kazumasa Yanagisawa , Yoshihiro Shinozaki , Hidetomo Aoyagi
IPC分类号： H01L21/3205 , G11C5/02 , G11C5/06 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/04 , H01L29/73
CPC分类号： G11C5/025 , G11C5/063
摘要： Outside-cell wiring that extends the upper part of a macro cell to the direction of X axis is composed of the wiring layer of the upper layer than a terminal for a signal of the macro cell and this terminal is formed to extend in the direction of Y axis (direction that intersects the direction of X axis) so that the outside-cell wiring can be secured for a plurality of wiring channels. The macro cell and the outside-cell wiring are connected via this signal terminal.
摘要翻译：将宏单元的上部延伸到X轴方向的外电池布线由与宏单元的信号的端子相比上层的布线层构成，该端子形成为沿着宏单元的方向延伸 Y轴（与X轴方向相交的方向），从而可以确保多个布线通道的外部单元布线。宏单元和外部单元布线通过该信号端子连接。

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