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1. 发明授权

US5304868A Non-inverting buffer circuit device and semiconductor memory circuit device 失效
标题翻译：同相缓冲电路器件和半导体存储器电路器件
公开(公告)号：US5304868A
公开(公告)日：1994-04-19
申请号：US783781
申请日：1991-10-29
申请人： Yuji Yokoyama , Kazuyuki Miyazawa , Hitoshi Miwa , Shoji Wada
发明人： Yuji Yokoyama , Kazuyuki Miyazawa , Hitoshi Miwa , Shoji Wada
IPC分类号： G11C11/409 , G11C7/10 , G11C8/06 , G11C11/417 , H03K19/013 , H03K19/0175 , H03K19/0944 , H03K19/02 , G11C8/00
CPC分类号： H03K19/0136 , G11C7/1051 , G11C8/06 , H03K19/09448
摘要： A non-inverting buffer circuit device suited for an input buffer circuit of a semiconductor memory is provided so that the number of logic gate stages can be reduced to realize a high speed operation. The circuit is designed in such a way that an MOS transistor at an input stage drives a bipolar transistor at an output stage to produce an output. An n-channel MOS transistor and a p-channel MOS transistor connected in parallel between the base and the collector of the bipolar transistor are on/off controlled by an inverted signal of the input digital signal and a non-inverted signal thereof, respectively. In another aspect, the input buffer circuit includes an inverted signal outputting circuit, and a non-inverted signal outputting circuit in the set mode the input signal in the non-inverted state and outputting in the reset mode the signal at the prescribed potential. The inverted signal outputting circuit includes a bipolar transistor producing an output signal at its collector potential, a first switching circuit for controlling supply of a collector current to the bipolar transistor, an n-channel MOS transistor, connected in parallel between the base and the collector of the bipolar transistor, for supplying a base current to the bipolar transistor in accordance with the input signal, and a second switching circuit for controlling supply of the base current to the bipolar transistor, wherein the first switching circuit and the second switching circuit are selectively on-off controlled.
摘要翻译：提供了适用于半导体存储器的输入缓冲电路的非反相缓冲电路装置，可以减少逻辑门级的数量，实现高速运算。该电路被设计成使得输入级的MOS晶体管在输出级驱动双极晶体管以产生输出。并联连接在双极型晶体管的基极和集电极之间的n沟道MOS晶体管和p沟道MOS晶体管分别通过输入数字信号的反相信号和非反相信号进行开/关控制。在另一方面，输入缓冲电路包括反相信号输出电路和非反相信号输出电路，在设定模式下输入处于非反相状态的输入信号，并以复位模式输出处于规定电位的信号。反相信号输出电路包括产生其集电极电位的输出信号的双极晶体管，用于控制向双极晶体管供给集电极电流的第一开关电路，并联在基极和集电极之间的n沟道MOS晶体管用于根据输入信号向双极晶体管提供基极电流;以及第二开关电路，用于控制对双极晶体管的基极电流的供应，其中第一开关电路和第二开关电路选择性地开关控制。

2. 发明授权

US4216628A Device for automatically grinding syringe needle point 失效
标题翻译：注射器针尖自动研磨的装置
公开(公告)号：US4216628A
公开(公告)日：1980-08-12
申请号：US947503
申请日：1978-10-02
申请人： Shoji Wada
发明人： Shoji Wada
IPC分类号： B24B19/16
CPC分类号： B24B19/16
摘要： An automatic grinder for grinding a syringe needle point includes a holder for holding a tube to be ground, a grinder, a hold-angle changer to change the angle at which the tube is held, a device to change the angular alignment of the tube by rotating the tube about its axis, a grinding volume changer to change the spacing between the holder and the grinder, a reciprocator to reciprocate the tube holder relative to the grinder for carrying out a grinding operation, a space adjuster to compensate for wear of the grinding surface in the grinder, and a grinding controller for automatic coordination of these units according to a preset program.
摘要翻译：用于研磨注射器针尖的自动研磨机包括用于保持要被研磨的管的保持器，研磨机，用于改变保持管的角度的保持角更换器，用于改变管的角度对准的装置旋转管绕其轴线，磨削体积更换器以改变保持器和研磨机之间的间隔，往复运动器使管夹相对于研磨机往复运动以进行研磨操作，空间调节器以补偿研磨磨损研磨机的表面，以及根据预设程序自动协调这些单元的磨削控制器。

3. 发明授权

US06084809A Main amplifier circuit and input-output bus for a dynamic random access memory 失效
标题翻译：主放大器电路和输入输出总线，用于动态随机存取存储器
公开(公告)号：US06084809A
公开(公告)日：2000-07-04
申请号：US988689
申请日：1997-12-11
申请人： Shoji Wada
发明人： Shoji Wada
IPC分类号： G01R31/28 , G11C7/00 , G11C7/10 , G11C11/401 , G11C11/407 , G11C11/409 , G11C11/4091 , G11C11/4096 , G11C29/00 , G11C29/12 , G11C29/34 , H01L21/8242 , H01L27/108
CPC分类号： G11C7/1078 , G11C11/4091 , G11C11/4096 , G11C29/34 , G11C7/1096
摘要： A semiconductor memory is provided with a main amplifier circuit that is capable of selectively driving and precharging two I/O buses in conjunction with a write amplifier. The main amplifier circuit includes a separation and precharge section and an activation section. The activation section drives a signal for activating the first section to precharge the two I/O signals only when the two I/O buses are not being separated. The main amplifier circuit also includes both a main output bus and a test output bus. In so doing, the semiconductor memory can operate in a normal mode and a test mode. In the test mode, twice as many memory cells of the semiconductor memory can be accessed simultaneously, thereby reducing test time. The semiconductor memory, which can be one of many different data widths, has different sized output buses associated with each data width. Output buses with a relatively large capacitance can be produced with a large width, giving them a relatively small resistance. Conversely, output buses with a relatively small capacitance can be produced with a small width, giving them a relatively large resistance. As a result, a time constant for the output buses associated with each of the different widths is very similar.
摘要翻译：半导体存储器设置有主放大器电路，其能够与写放大器一起选择性地驱动和预充电两个I / O总线。主放大器电路包括分离和预充电部分和激活部分。激活部分驱动用于激活第一部分的信号，以便仅当两个I / O总线未被分离时才对两个I / O信号进行预充电。主放大器电路还包括主输出总线和测试输出总线。这样做，半导体存储器可以在正常模式和测试模式下工作。在测试模式下，可以同时访问半导体存储器的两倍的存储单元，从而减少测试时间。可以是许多不同数据宽度之一的半导体存储器具有与每个数据宽度相关联的不同尺寸的输出总线。可以产生具有较大电容的输出总线，具有较大的宽度，使它们具有较小的电阻。相反，具有相对小的电容的输出总线可以以较小的宽度产生，给它们相对较大的电阻。结果，与每个不同宽度相关联的输出总线的时间常数非常相似。

4. 发明授权

US5946245A Memory array test circuit and method 失效
标题翻译：内存阵列测试电路及方法
公开(公告)号：US5946245A
公开(公告)日：1999-08-31
申请号：US980098
申请日：1997-11-26
申请人： David R. Brown , Shoji Wada
发明人： David R. Brown , Shoji Wada
IPC分类号： G01R31/28 , G11C11/401 , G11C29/12 , G11C29/38 , G11C29/40 , G11C29/44 , G11C7/00
CPC分类号： G11C29/40 , G11C29/38 , G11C29/44
摘要： A circuit for testing a memory cell array 100. The circuit includes a test circuit 104 coupled to the array and includes a data output line 106 and a failure signal output line 108. A shift register 110, which includes a plurality of latches, a clock signal input 114, and an output line 116, is connected to the failure signal output line of the test circuit. The circuit also includes a three-state output buffer driver 118, the buffer driver including a data input line, a failure signal input line, and a data output line. The failure signal line of the buffer driver is connected to the output line of the shift register 110. Upon detecting a defective memory cell in the array, the test circuit produces a failure signal on the failure signal output line 116 of the test circuit. The failure signal is then sent to the shift register 110 causing the buffer driver 118 to enter a high-impedance state in response to said failure signal. The shift register 110 comprises a number of latches in accordance with the desired latency variability of the system or test equipment using the test circuit.
摘要翻译：用于测试存储单元阵列100的电路。该电路包括耦合到阵列的测试电路104，并包括数据输出线106和故障信号输出线108.移位寄存器110包括多个锁存器，时钟信号输入114和输出线116连接到测试电路的故障信号输出线。该电路还包括三态输出缓冲器驱动器118，缓冲器驱动器包括数据输入线，故障信号输入线和数据输出线。缓冲驱动器的故障信号线连接到移位寄存器110的输出线。在检测到阵列中的有缺陷的存储单元时，测试电路在测试电路的故障信号输出线116上产生故障信号。故障信号然后被发送到移位寄存器110，导致缓冲器驱动器118响应于所述故障信号而进入高阻抗状态。移位寄存器110包括根据使用测试电路的系统或测试设备的期望的等待时间变化性的多个锁存器。

5. 发明授权

US4430358A Method of manufacturing a cut tube to be used for syringe needles 失效
标题翻译：制造用于注射针的切割管的方法
公开(公告)号：US4430358A
公开(公告)日：1984-02-07
申请号：US327737
申请日：1981-12-04
申请人： Shoji Wada
发明人： Shoji Wada
IPC分类号： A61M5/32 , B21G1/08 , B65B33/00
CPC分类号： B21G1/08 , Y10S128/21
摘要： A simple and efficient method of manufacturing a syringe needle is provided herein, which involves spreading a resin solution on the entire inside and outside of a cut stainless steel tube having the dimensions of a syringe needle, hardening the resin on the inside and outside of said cut tube, removing the hardened resin from the outside of the cut tube, grinding one end of the tube with a grinder to form a main bevel, changing the contact angle between the grinder and the cut tube to form side bevels to produce a syringe needle tube having a piercing point at the ground edge of said tube, and washing away grinding materials and pollutants from the tube.
摘要翻译：本发明提供了一种制造注射针的简单而有效的方法，其中包括在具有注射器针的尺寸的切割的不锈钢管的整个内部和外侧扩展树脂溶液，使所述树脂的内部和外部硬化树脂切割管，从切割管的外部去除硬化树脂，用研磨机研磨管的一端以形成主斜面，改变研磨机和切割管之间的接触角以形成侧斜面以产生注射器针管在所述管的地面边缘处具有刺穿点，并且从管中洗掉研磨材料和污染物。

6. 发明申请

US20080304772A1 Hydrostatic guide system 审中-公开
标题翻译：静压导向系统
公开(公告)号：US20080304772A1
公开(公告)日：2008-12-11
申请号：US12156758
申请日：2008-06-04
申请人： Osamu Kakutani , Yutaka Kondo , Shoji Wada
发明人： Osamu Kakutani , Yutaka Kondo , Shoji Wada
IPC分类号： F16C32/06
CPC分类号： F16C29/025 , F16C29/12 , F16C32/0402 , F16C32/06 , F16C32/0603 , F16C32/0674
摘要： A hydrostatic guide system including a guide table, a transfer table, a floating amount sensor attached to the transfer table, and a control unit. The transfer table has an inner portion, in which a magnetic attraction unit including a yoke and an electromagnet is embedded, and an outer shell portion, which covers the side surface and the upper surface of the inner portion. After the inner portion houses the yoke and the electromagnet, a gap around the yoke and the electromagnet is filled with a material having appropriate strength, so that the inner portion is integrated with the outer shell portion, and the transfer surface is flattened as whole. A surrounding groove is provided around the transfer table, and pressurized fluid supplied into the groove is jetted out to the guide table.
摘要翻译：一种静压导向系统，包括导向台，转印台，附接到转印台的浮动量传感器和控制单元。转印台具有嵌入有包括磁轭和电磁体的磁性吸引单元的内部部分和覆盖内侧部分的侧表面和上表面的外壳部分。在内部容纳磁轭和电磁体之后，通过具有适当强度的材料填充磁轭和电磁体周围的间隙，使得内部与外壳部分一体化，并且转印表面整体变平。在转印台周围设置有周围的槽，并且供给到槽中的加压流体喷射到导向台。

7. 发明授权

US6166977A Address controlled sense amplifier overdrive timing for semiconductor memory device 有权
标题翻译：半导体存储器件的地址控制读出放大器过驱动定时
公开(公告)号：US6166977A
公开(公告)日：2000-12-26
申请号：US272872
申请日：1999-03-19
申请人： Ken Saitoh , Shoji Wada
发明人： Ken Saitoh , Shoji Wada
IPC分类号： G11C7/06 , G11C7/22 , G11C11/4091 , G11C7/00
CPC分类号： G11C11/4091 , G11C7/06 , G11C7/22
摘要： A dynamic random access memory device having a number of sense amplifier banks (404a-404h) is disclosed. Each sense amplifier bank (404a-404h) has an associated memory array (402a-402h) and supply switch (406a-406h). In a given sense operation, data signals are coupled from a memory array (402a-402h) to its associated sense amplifier bank (404a-404h). Selection of the memory array (402a-402h) is determined by address signals (MS0-MS7). The supply switches (406a-406h) provide a sense amplifier supply voltage at a supply node (708) of its associated sense amplifier bank (404a-404h). At the initial portion of a sense operation, the supply switch (406a-406h) couples the high power supply voltage (VDD) to its associated supply node (708). After a predetermined time period, the supply switch couples a reduced array voltage (VDL) to its associated supply node (708). The switching operation is determined by an overdrive signal (SAOV). The timing of the SAOV signal is based upon the location of the memory array (402a-402h) which is being accessed in the sense operation.
摘要翻译：公开了一种具有多个读出放大器组（404a-404h）的动态随机存取存储器件。每个读出放大器组（404a-404h）具有相关联的存储器阵列（402a-402h）和电源开关（406a-406h）。在给定的感测操作中，数据信号从存储器阵列（402a-402h）耦合到其相关联的读出放大器组（404a-404h）。存储器阵列（402a-402h）的选择由地址信号（MS0-MS7）确定。电源开关（406a-406h）在其相关读出放大器组（404a-404h）的电源节点（708）处提供感测放大器电源电压。在感测操作的初始部分，电源开关（406a-406h）将高电源电压（VDD）耦合到其相关联的电源节点（708）。在预定时间段之后，电源开关将降低的阵列电压（VDL）耦合到其相关联的电源节点（708）。切换操作由过驱动信号（SAOV）决定。 SAOV信号的定时基于在感测操作中被访问的存储器阵列（402a-402h）的位置。

8. 发明授权

US5831925A Memory configuration circuit and method 失效
标题翻译：内存配置电路和方法
公开(公告)号：US5831925A
公开(公告)日：1998-11-03
申请号：US982672
申请日：1997-12-02
申请人： David R. Brown , Shoji Wada , Kazuya Ito , Yasuhito Ichimura , Ken Saitoh
发明人： David R. Brown , Shoji Wada , Kazuya Ito , Yasuhito Ichimura , Ken Saitoh
IPC分类号： G11C11/41 , G06F12/06 , G11C7/10 , G11C8/12 , G11C11/401 , G11C8/00 , G11C7/00
CPC分类号： G11C8/12 , G11C7/1045
摘要： A memory circuit includes a bond option circuit 106 having an input and an output, and row control circuitry 100 coupled to the output of the bond option circuit, the row control circuitry including address terminals, A12 and A13. The memory circuit also includes column control circuitry 102 coupled to the output of the bond option circuit, the column control circuitry 102 also including address terminals, A12 and A13. A memory cell array is coupled to the row control and column control circuitry and is arranged in a first plurality of banks of memory cells, the banks being selectable by a combination of address signals on the address terminals of the row control and column control circuitry. In response to a first signal at the input of the bond option circuit 106, the bond option circuit produces a second signal at the output of the bond option circuit that is coupled to the row control 100 and column control 102 circuitry. In response to the second signal, the row control and column control circuitry makes the banks of the array selectable in a second plurality. For example, the array may originally be arranged in four banks, but by the placing the proper signal at the input of the bond option circuit, the array is selectable as a two-bank array.
摘要翻译：存储器电路包括具有输入和输出的接合选择电路106，以及耦合到接合选择电路的输出的行控制电路100，行控制电路包括地址端子A12和A13。存储器电路还包括耦合到键选择电路的输出的列控制电路102，列控制电路102还包括地址端子A12和A13。存储单元阵列耦合到行控制和列控制电路，并且被布置在第一多个存储单元组中，这些存储体可以由行控制和列控制电路的地址端上的地址信号的组合来选择。响应于接合选择电路106的输入处的第一信号，接合选择电路在耦合到行控制器100和列控制器102电路的接合选择电路的输出处产生第二信号。响应于第二信号，行控制和列控制电路使得阵列的组可选择在第二组中。例如，阵列最初可以排列成四个组，但是通过将适当的信号放置在键合选项电路的输入处，阵列可以选择为双组阵列。

9. 发明授权

US5506804A Dynamic Random Access Type Semiconductor Device 失效
标题翻译：动态随机存取型半导体器件
公开(公告)号：US5506804A
公开(公告)日：1996-04-09
申请号：US159205
申请日：1993-11-30
申请人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
发明人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
IPC分类号： G11C11/409 , G05F3/24 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C29/80 , G11C11/4085 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , G11C11/401
摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.
摘要翻译：提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。读取信号作为电流信号传输，然后转换为电压信号，以提高读取速度。此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

10. 发明授权

US5276648A Testing method for a semiconductor memory device 失效
标题翻译：半导体存储器件的测试方法
公开(公告)号：US5276648A
公开(公告)日：1994-01-04
申请号：US818274
申请日：1992-01-08
申请人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
发明人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
IPC分类号： G11C11/409 , G05F3/24 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C29/80 , G11C11/4085 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , G11C11/401
摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.
摘要翻译：提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。读取信号作为电流信号传输，然后转换为电压信号，以提高读取速度。此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

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