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1. 发明申请

US20050243588A1 Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same 有权
标题翻译：数据信号线驱动电路，驱动电路，并入其的图像显示装置，以及使用该数据信号线的电子装置
公开(公告)号：US20050243588A1
公开(公告)日：2005-11-03
申请号：US11091012
申请日：2005-03-25
申请人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
发明人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
IPC分类号： G09G3/20 , G09G3/36 , G09G5/00 , H01L21/77 , H01L21/84 , G11C5/06
CPC分类号： G09G3/2011 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G5/005 , G09G5/006 , G09G2300/0456 , G09G2310/0205 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2320/0626 , G09G2330/021 , G09G2340/0428 , G09G2340/10 , G09G2340/12 , G09G2360/144 , H01L27/124 , H04N2007/145
摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.
摘要翻译：图像显示装置包括两个数据信号线驱动电路和彼此不同地配置的两个扫描信号线驱动电路。不同的数据信号线驱动电路和扫描信号线驱动电路兼容不同的显示格式。可以以最合适的显示格式生产显示器，并且可以通过根据输入视频的类型和环境条件的开关操作驱动电路来降低功耗。此外，通过使用多个驱动电路将视频信号以时间滞后的方式写入信号线，可以在另一图像上写入图像; 因此，可以在不外部处理视频信号的情况下产生叠加显示。因此，可以在图像显示装置中实现令人满意的图像显示和低功耗。

2. 发明申请

US20070146354A1 Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same 审中-公开
公开(公告)号：US20070146354A1
公开(公告)日：2007-06-28
申请号：US11634738
申请日：2006-12-05
申请人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
发明人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
IPC分类号： G09G5/00 , G06F3/038
CPC分类号： G09G3/2011 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G5/005 , G09G5/006 , G09G2300/0456 , G09G2310/0205 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2320/0626 , G09G2330/021 , G09G2340/0428 , G09G2340/10 , G09G2340/12 , G09G2360/144 , H01L27/124 , H04N2007/145
摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.

3. 发明申请

US20060181502A1 Signal line driving circuit and image display device 审中-公开
公开(公告)号：US20060181502A1
公开(公告)日：2006-08-17
申请号：US11402352
申请日：2006-04-11
申请人： Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Graham Cairns , Michael Brownlow
发明人： Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Graham Cairns , Michael Brownlow
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2310/0289
摘要： A signal line driving circuit includes a shift register having a plurality of shift circuits, each of which shifts a start pulse successively to the next stage, synchronizing with the timing of a clock signal. In this signal line driving circuit, shift pulses are outputted from an AND gate based on output pulses of two adjacent shift circuits. Meanwhile, a width specifying pulse for specifying a pulse width of the shift pulse is inputted via a transistor whose ON/OFF operation is controlled by the shift pulse. A logical operation circuit operates an AND of the shift pulse and the width specifying pulse and outputs the result of operation to a signal line. When the shift pulse is non-active, the transistor becomes OFF, which causes the signal line transmitting the width specifying pulse to be disconnected from the signal line driving circuit, thereby reducing a capacitive load of wiring. As a result, reduction of a parasitic capacitance of the wiring, reduction in the number of elements, reduction in the size of an amplitude of an input signal, etc. in the signal line driving circuit are attained.

4. 发明申请

US20050184784A1 Flip-flops, shift registers, and active-matrix display devices 有权
标题翻译：触发器，移位寄存器和有源矩阵显示设备
公开(公告)号：US20050184784A1
公开(公告)日：2005-08-25
申请号：US11043178
申请日：2005-01-27
申请人： Hajime Washio , Yuhichiroh Murakami , Michael Brownlow
发明人： Hajime Washio , Yuhichiroh Murakami , Michael Brownlow
IPC分类号： G02F1/133 , G09G3/20 , G09G3/30 , G09G3/36 , G11C11/412 , G11C19/00 , H03K3/012 , H03K3/037 , H03K3/356 , H03K23/00 , H03K3/289
CPC分类号： H03K3/356165 , G09G3/3677 , G09G3/3688 , G11C19/00 , H03K3/012 , H03K3/356113 , H03K3/356147
摘要： A latch section includes a latch circuit. The latch circuit includes inverters and latches an input signal from a gating section. Between one of the inverters of the latch circuit and the output terminal OUT is disposed an analog switch whose ON/OFF characteristics are switched according to High/Low of a reset signal. Between the output terminal and an input for receiving a low potential as a power supply of a flip-flop is disposed a switching element whose ON/OFF characteristics are switched according to High/Low of the reset signal.
摘要翻译：锁存部分包括锁存电路。锁存电路包括反相器并锁存来自门控部分的输入信号。在锁存电路的一个反相器和输出端子OUT之间设置有根据复位信号的高/低切换开/关特性的模拟开关。在输出端子和用于接收作为触发器的电源的低电位的输入端之间设置有根据复位信号的高/低切换开/关特性的开关元件。

5. 发明授权

US07158109B2 Active matrix display 失效
标题翻译：主动矩阵显示
公开(公告)号：US07158109B2
公开(公告)日：2007-01-02
申请号：US10236033
申请日：2002-09-04
申请人： Graham Cairns , Michael Brownlow
发明人： Graham Cairns , Michael Brownlow
IPC分类号： G09G5/00
CPC分类号： G09G3/36 , G09G3/3648
摘要： An active matrix display comprises an active matrix array of pixels divided into first and second sets, the pixels 35 of the first set are refreshed in the conventional active matrix way by a first refreshing arrangement M1, 6, 7. Pixels 36 for displaying a graphical feature such as an icon overlaid on the active matrix display image have a second refreshing arrangement M2, 6, 37 to allow the icon pixels of each icon to be switched to the same state, such as maximum back or maximum white. The icon pixels 36 may also have the first refreshing arrangement M1, 6, 7 so that they can be used either as part of the active matrix for displaying arbitrary data or when selected as such, for overlaying the icon image on the arbitrary image data.
摘要翻译：有源矩阵显示器包括被划分为第一和第二组的像素的有源矩阵阵列，第一组的像素35通过第一刷新装置M1,6,7以常规有源矩阵方式刷新。用于显示诸如重叠在有源矩阵显示图像上的图标的图形特征的像素36具有第二刷新装置M 2,6,37，以允许每个图标的图标像素切换到相同的状态，诸如最大背面或最大白。图标像素36还可以具有第一刷新装置M 1，6，7，使得它们可以用作用于显示任意数据的有源矩阵的一部分，或者当被选择时，用于将图标图像叠加在任意图像数据上。

6. 发明申请

US20060148137A1 Integrated MEMS packaging 有权
标题翻译：集成MEMS封装
公开(公告)号：US20060148137A1
公开(公告)日：2006-07-06
申请号：US11178148
申请日：2005-07-08
申请人： John Hartzell , Harry Walton , Michael Brownlow
发明人： John Hartzell , Harry Walton , Michael Brownlow
IPC分类号： H01L21/84
CPC分类号： B81C1/0023 , H01L27/1214
摘要： An integrated MEMS package and associated packaging method are provided. The method includes: forming an electrical circuit, electrically connected to the first substrate; integrating a MEMS device on a first substrate region, electrically connected to the first substrate; providing a second substrate overlying the first substrate; and, forming a wall along the first region boundaries, between the first and second substrate. In one aspect, the electrical circuit is formed using thin-film processes; and, wherein integrating the MEMS device on the first substrate region includes forming the MEMS using thin-film processes, simultaneous with the formation of the electrical device. Alternately, the MEMS device is formed in a separate process, attached to the first substrate, and electrical interconnections are formed to the first substrate using thin-film processes.
摘要翻译：提供集成MEMS封装和相关封装方法。该方法包括：形成电连接到第一基板的电路; 将MEMS器件集成在电连接到第一衬底的第一衬底区域上; 提供覆盖所述第一基板的第二基板; 以及沿所述第一区域边界在所述第一和第二基板之间形成壁。在一个方面，使用薄膜工艺形成电路; 并且其中将MEMS器件集成在第一衬底区域上包括使用薄膜工艺形成MEMS，同时形成电子器件。或者，MEMS器件以独立的工艺形成，附接到第一衬底，并且使用薄膜工艺将电互连形成到第一衬底。

7. 发明申请

US20070099327A1 Method for integrated MEMS packaging 有权
标题翻译：集成MEMS封装的方法
公开(公告)号：US20070099327A1
公开(公告)日：2007-05-03
申请号：US11640592
申请日：2006-12-18
申请人： John Hartzell , Harry Walton , Michael Brownlow
发明人： John Hartzell , Harry Walton , Michael Brownlow
IPC分类号： H01L21/00
CPC分类号： B81C1/0023 , H01L27/1214
摘要： An integrated MEMS package and associated packaging method are provided. The method includes: forming an electrical circuit, electrically connected to the first substrate; integrating a MEMS device on a first substrate region, electrically connected to the first substrate; providing a second substrate overlying the first substrate; and, forming a wall along the first region boundaries, between the first and second substrate. In one aspect, the electrical circuit is formed using thin-film processes; and, wherein integrating the MEMS device on the first substrate region includes forming the MEMS using thin-film processes, simultaneous with the formation of the electrical device. Alternately, the MEMS device is formed in a separate process, attached to the first substrate, and electrical interconnections are formed to the first substrate using thin-film processes.
摘要翻译：提供集成MEMS封装和相关封装方法。该方法包括：形成电连接到第一基板的电路; 将MEMS器件集成在电连接到第一衬底的第一衬底区域上; 提供覆盖所述第一基板的第二基板; 以及沿所述第一区域边界在所述第一和第二基板之间形成壁。在一个方面，使用薄膜工艺形成电路; 并且其中将MEMS器件集成在第一衬底区域上包括使用薄膜工艺形成MEMS，同时形成电子器件。或者，MEMS器件以独立的工艺形成，附接到第一衬底，并且使用薄膜工艺将电互连形成到第一衬底。

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