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1. 发明申请

US20050243588A1 Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same 有权
标题翻译：数据信号线驱动电路，驱动电路，并入其的图像显示装置，以及使用该数据信号线的电子装置
公开(公告)号：US20050243588A1
公开(公告)日：2005-11-03
申请号：US11091012
申请日：2005-03-25
申请人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
发明人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
IPC分类号： G09G3/20 , G09G3/36 , G09G5/00 , H01L21/77 , H01L21/84 , G11C5/06
CPC分类号： G09G3/2011 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G5/005 , G09G5/006 , G09G2300/0456 , G09G2310/0205 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2320/0626 , G09G2330/021 , G09G2340/0428 , G09G2340/10 , G09G2340/12 , G09G2360/144 , H01L27/124 , H04N2007/145
摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.
摘要翻译：图像显示装置包括两个数据信号线驱动电路和彼此不同地配置的两个扫描信号线驱动电路。不同的数据信号线驱动电路和扫描信号线驱动电路兼容不同的显示格式。可以以最合适的显示格式生产显示器，并且可以通过根据输入视频的类型和环境条件的开关操作驱动电路来降低功耗。此外，通过使用多个驱动电路将视频信号以时间滞后的方式写入信号线，可以在另一图像上写入图像; 因此，可以在不外部处理视频信号的情况下产生叠加显示。因此，可以在图像显示装置中实现令人满意的图像显示和低功耗。

2. 发明申请

US20070146354A1 Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same 审中-公开
公开(公告)号：US20070146354A1
公开(公告)日：2007-06-28
申请号：US11634738
申请日：2006-12-05
申请人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
发明人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
IPC分类号： G09G5/00 , G06F3/038
CPC分类号： G09G3/2011 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G5/005 , G09G5/006 , G09G2300/0456 , G09G2310/0205 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2320/0626 , G09G2330/021 , G09G2340/0428 , G09G2340/10 , G09G2340/12 , G09G2360/144 , H01L27/124 , H04N2007/145
摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.

3. 发明申请

US20060181502A1 Signal line driving circuit and image display device 审中-公开
公开(公告)号：US20060181502A1
公开(公告)日：2006-08-17
申请号：US11402352
申请日：2006-04-11
申请人： Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Graham Cairns , Michael Brownlow
发明人： Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Graham Cairns , Michael Brownlow
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2310/0289
摘要： A signal line driving circuit includes a shift register having a plurality of shift circuits, each of which shifts a start pulse successively to the next stage, synchronizing with the timing of a clock signal. In this signal line driving circuit, shift pulses are outputted from an AND gate based on output pulses of two adjacent shift circuits. Meanwhile, a width specifying pulse for specifying a pulse width of the shift pulse is inputted via a transistor whose ON/OFF operation is controlled by the shift pulse. A logical operation circuit operates an AND of the shift pulse and the width specifying pulse and outputs the result of operation to a signal line. When the shift pulse is non-active, the transistor becomes OFF, which causes the signal line transmitting the width specifying pulse to be disconnected from the signal line driving circuit, thereby reducing a capacitive load of wiring. As a result, reduction of a parasitic capacitance of the wiring, reduction in the number of elements, reduction in the size of an amplitude of an input signal, etc. in the signal line driving circuit are attained.

4. 发明申请

US20080036753A1 Display device and driving method thereof 有权
标题翻译：显示装置及其驱动方法
公开(公告)号：US20080036753A1
公开(公告)日：2008-02-14
申请号：US11882533
申请日：2007-08-02
申请人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
发明人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
IPC分类号： G06F3/038
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3648 , G09G3/3666 , G09G3/3677 , G09G2310/0213 , G09G2310/0232 , G09G2310/027 , G09G2310/0283 , G09G2310/0297 , G09G2310/04 , G09G2320/0214 , G09G2320/10 , G09G2330/021
摘要： An example control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area are refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.
摘要翻译：用于控制写入像素PIX的示例性控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD 2写入用于非显示区域的电压VB或电压VW，不仅在第一帧中显示，而且在预定数量的帧中显示一次。换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷，可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时限制功耗。

5. 发明授权

US06618043B2 Image display device and image display method 有权
公开(公告)号：US06618043B2
公开(公告)日：2003-09-09
申请号：US09504418
申请日：2000-02-15
申请人： Hajime Washio , Yasushi Kubota , Yasuyoshi Kaise , Tamotsu Sakai , Kazuhiro Maeda
发明人： Hajime Washio , Yasushi Kubota , Yasuyoshi Kaise , Tamotsu Sakai , Kazuhiro Maeda
IPC分类号： G09G500
CPC分类号： G09G3/3648 , G09G2310/0248 , G09G2330/021
摘要： A precharge circuit is composed of (a) a reference signal input section, to which at least one precharge reference potential is inputted, (b) a control signal input section, to which at least one control signal is inputted, (c) a plurality of signal delay sections for sequentially delaying an output of the control signal input section, and (d) a reference signal switching section for switching, in accordance with outputs of the signal delay sections, between a state of outputting the precharge reference potential of the reference signal input section to each of the data signal lines and a state of non-outputting the same thereto. With this arrangement, the precharge control signal is sequentially delayed within the precharge circuit by the delay circuits composed of inverter circuits or the like, so that timings at which the precharge reference potential is written in the data signal lines are dispersed. By sequentially delaying the control signal within the precharge circuit, reduction of power consumption and excellent image display are realized.

6. 发明授权

US06580411B1 Latch circuit, shift register circuit and image display device operated with a low consumption of power 有权
标题翻译：锁存电路，移位寄存器电路和图像显示设备以低功耗运行
公开(公告)号：US06580411B1
公开(公告)日：2003-06-17
申请号：US09300178
申请日：1999-04-27
申请人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
发明人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
IPC分类号： G09G336
CPC分类号： H03K3/356121 , G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2310/0286 , G09G2320/0209 , G09G2320/0257 , G09G2330/021 , H03K3/356139
摘要： If a clock signal ck is “H” and an input pulse signal in (first control signal) is “H”, then n-type transistors M15 and M16 are turned on to make an output node/OUT have the GND level. Then, a p-type transistor M12 is turned on to make an output node OUT have a Vcc (16 V) level. Thus, a latch circuit LAT operates as a level shifter circuit when first and second control signals and the clock signal ck are at “H” and operates as a level hold circuit in any other case. Therefore, the shift register circuit constructed of the latch circuit LAT functions as a low-voltage interface, and the input of the clock signal ck is stopped when the latch circuit LAT is inactive, so that the load and the consumption of power of the clock signal line are reduced.
摘要翻译：如果时钟信号ck为“H”，并且（第一控制信号）中的输入脉冲信号为“H”，则n型晶体管M15和M16导通，使输出节点/ OUT具有GND电平。然后，p型晶体管M12导通，使得输出节点OUT具有Vcc（16V）电平。因此，当第一和第二控制信号和时钟信号ck处于“H”时，锁存电路LAT作为电平移位器电路工作，并且在任何其它情况下作为电平保持电路工作。因此，由锁存电路LAT构成的移位寄存器电路用作低电压接口，并且当锁存电路LAT不活动时，时钟信号ck的输入停止，使得时钟的负载和功率的消耗信号线减少。

7. 发明授权

US07196699B1 Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power 有权
标题翻译：锁存电路，移位寄存器电路，逻辑电路和图像显示设备以低功耗运行
公开(公告)号：US07196699B1
公开(公告)日：2007-03-27
申请号：US09506033
申请日：2000-02-16
申请人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
发明人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
IPC分类号： G09G5/00 , G09G3/26 , H03K19/0175 , H03K19/00 , H03K5/153
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/0417 , G09G2310/021 , G09G2310/0289 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.
摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。

8. 发明授权

US07079096B2 Image display device and display driving method 失效
公开(公告)号：US07079096B2
公开(公告)日：2006-07-18
申请号：US10253570
申请日：2002-09-24
申请人： Hajime Washio , Yasuyoshi Kaise , Kazuhiro Maeda , Yasushi Kubota
发明人： Hajime Washio , Yasuyoshi Kaise , Kazuhiro Maeda , Yasushi Kubota
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G3/3614 , G09G3/3688 , G09G2310/0248
摘要： Before a potential of counter electrode is changed, a potential holding circuit fixedly holds potentials of data signal lines S during a non-selective period of scanning signal lines G. This prevents the potentials of the data signal lines S from being an undesirably large potential, which is caused by coupling capacitors between the counter electrode and each data signal line S, whereby it is possible to supply to the pixel capacitor an electric charge corresponding to a gradation to be displayed, by using the relatively low potentials of the data signal lines S. This lowers a power supply voltage of a data signal driving circuit SD, thus reducing the electric power consumption. In short, with this arrangement, a liquid crystal display device can perform an opposed AC drive for line-inversion drive, frame-inversion drive and the like, by low power supply voltage of the data signal line driving circuit SD, thereby reducing the electric power consumption.

9. 发明授权

US06940500B2 Image display device and display driving method 有权
标题翻译：图像显示装置和显示驱动方法
公开(公告)号：US06940500B2
公开(公告)日：2005-09-06
申请号：US10252497
申请日：2002-09-23
申请人： Hajime Washio , Yasuyoshi Kaise , Kazuhiro Maeda , Yasushi Kubota
发明人： Hajime Washio , Yasuyoshi Kaise , Kazuhiro Maeda , Yasushi Kubota
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G09G5/00
CPC分类号： G09G3/3648 , G09G3/3688 , G09G2310/0248 , G09G2330/021
摘要： A potential of a data signal line S during a scanning period is charged to a substantially intermediate potential of a data signal at a corresponding frame. Thus, extremely large dispersion does not occur in a potential of each pixel capacitor with respect to a potential of the data signal line S, so that it is possible to restrict dispersion of a leak current flowing via an active element of each pixel. Thus, potential variation of a pixel PIX is reduced, so that it is possible to improve display quality during a non-scanning period. That is, in an active-matrix-type liquid crystal display, when a frame frequency is reduced by setting the non-scanning period to be sufficiently larger than a scanning period while a standby image is being displayed so as to realize low power consumption, the display quality is improved.
摘要翻译：扫描周期期间的数据信号线S的电位被充电到相应帧的数据信号的大致中间电位。因此，相对于数据信号线S的电位，每个像素电容器的电位不会发生极大的色散，从而可以限制流过每个像素的有源元件的漏电流的色散。因此，像素PIX的电位变化减小，使得可以在非扫描期间提高显示质量。也就是说，在有源矩阵型液晶显示器中，当通过在显示待机图像的同时将非扫描周期设置为比扫描周期充分大来降低帧频，从而实现低功耗，显示质量得到提高。

10. 发明申请

US20050057556A1 Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power 有权
标题翻译：锁存电路，移位寄存器电路，逻辑电路和图像显示设备以低功耗运行
公开(公告)号：US20050057556A1
公开(公告)日：2005-03-17
申请号：US10949990
申请日：2004-09-23
申请人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
发明人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/0417 , G09G2310/021 , G09G2310/0289 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.
摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。

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