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1. 发明授权

US08039336B2 Semiconductor device and method of fabrication thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08039336B2
公开(公告)日：2011-10-18
申请号：US12915683
申请日：2010-10-29
申请人： Yasuki Morino , Yoshihiko Kusakabe , Ryuichi Wakahara
发明人： Yasuki Morino , Yoshihiko Kusakabe , Ryuichi Wakahara
IPC分类号： H01L21/8232
CPC分类号： H01L21/28273 , H01L21/76232 , H01L27/115 , H01L27/11521
摘要： A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.
摘要翻译：一种方法包括以下步骤：将绝缘膜引入沟槽以提供沟槽隔离; 平坦化沟槽隔离以暴露钝化膜; 以及去除所述钝化膜并在第一硅层上沉积第二硅层和所述沟槽隔离; 并且在沉积第一硅层的步骤中，第一硅层是未掺杂的硅层，并且在沉积第二硅层的步骤中，第二硅层是掺杂硅层或随后具有引入杂质的未掺杂硅层，或并且通过随后的热滞后热扩散到第一硅层中。

2. 发明申请

US20100099234A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100099234A1
公开(公告)日：2010-04-22
申请号：US12643646
申请日：2009-12-21
申请人： Yasuki MORINO , Yoshihiko Kusakabe , Ryuichi Wakahara
发明人： Yasuki MORINO , Yoshihiko Kusakabe , Ryuichi Wakahara
IPC分类号： H01L21/762
CPC分类号： H01L21/28273 , H01L21/76232 , H01L27/115 , H01L27/11521
摘要： A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.
摘要翻译：一种方法包括以下步骤：将绝缘膜引入沟槽以提供沟槽隔离; 平坦化沟槽隔离以暴露钝化膜; 以及去除所述钝化膜并在第一硅层上沉积第二硅层和所述沟槽隔离; 并且在沉积第一硅层的步骤中，第一硅层是未掺杂的硅层，并且在沉积第二硅层的步骤中，第二硅层是掺杂硅层或随后具有引入杂质的未掺杂硅层，或并且通过随后的热滞后热扩散到第一硅层中。

3. 发明申请

US20080290453A1 Semiconductor device and method of fabrication thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080290453A1
公开(公告)日：2008-11-27
申请号：US12219402
申请日：2008-07-22
申请人： Yasuki Morino , Yoshihiko Kusakabe , Ryuichi Wakahara
发明人： Yasuki Morino , Yoshihiko Kusakabe , Ryuichi Wakahara
IPC分类号： H01L29/00
CPC分类号： H01L21/28273 , H01L21/76232 , H01L27/115 , H01L27/11521
摘要： A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.
摘要翻译：一种方法包括以下步骤：将绝缘膜引入沟槽以提供沟槽隔离; 平坦化沟槽隔离以暴露钝化膜; 以及去除所述钝化膜并在第一硅层上沉积第二硅层和所述沟槽隔离; 并且在沉积第一硅层的步骤中，第一硅层是未掺杂的硅层，并且在沉积第二硅层的步骤中，第二硅层是掺杂硅层或随后具有引入杂质的未掺杂硅层，或并且通过随后的热滞后热扩散到第一硅层中。

4. 发明申请

US20050287777A1 Semiconductor device and method of fabrication thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050287777A1
公开(公告)日：2005-12-29
申请号：US11159389
申请日：2005-06-23
申请人： Yasuki Morino , Yoshihiko Kusakabe , Ryuichi Wakahara
发明人： Yasuki Morino , Yoshihiko Kusakabe , Ryuichi Wakahara
IPC分类号： H01L21/00 , H01L21/04 , H01L21/28 , H01L21/762 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L21/76232 , H01L27/115 , H01L29/40114
摘要： A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.
摘要翻译：一种方法包括以下步骤：将绝缘膜引入沟槽以提供沟槽隔离; 平坦化沟槽隔离以暴露钝化膜; 以及去除所述钝化膜并在第一硅层上沉积第二硅层和所述沟槽隔离; 并且在沉积第一硅层的步骤中，第一硅层是未掺杂的硅层，并且在沉积第二硅层的步骤中，第二硅层是掺杂硅层或随后具有引入杂质的未掺杂硅层，或并且通过随后的热滞后热扩散到第一硅层中。

5. 发明授权

US07846788B2 Semiconductor device and method of fabrication thereof 有权
公开(公告)号：US07846788B2
公开(公告)日：2010-12-07
申请号：US12643646
申请日：2009-12-21
申请人： Yasuki Morino , Yoshihiko Kusakabe , Ryuichi Wakahara
发明人： Yasuki Morino , Yoshihiko Kusakabe , Ryuichi Wakahara
IPC分类号： H01L21/8232
CPC分类号： H01L21/28273 , H01L21/76232 , H01L27/115 , H01L27/11521
摘要： A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.

6. 发明授权

US07646055B2 Semiconductor device and method of fabrication thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07646055B2
公开(公告)日：2010-01-12
申请号：US12219402
申请日：2008-07-22
申请人： Yasuki Morino , Yoshihiko Kusakabe , Ryuichi Wakahara
发明人： Yasuki Morino , Yoshihiko Kusakabe , Ryuichi Wakahara
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L21/76232 , H01L27/115 , H01L27/11521
摘要： A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.
摘要翻译：一种方法包括以下步骤：将绝缘膜引入沟槽以提供沟槽隔离; 平坦化沟槽隔离以暴露钝化膜; 以及去除所述钝化膜并在第一硅层上沉积第二硅层和所述沟槽隔离; 并且在沉积第一硅层的步骤中，第一硅层是未掺杂的硅层，并且在沉积第二硅层的步骤中，第二硅层是掺杂硅层或随后具有引入杂质的未掺杂硅层，或并且通过随后的热滞后热扩散到第一硅层中。

7. 发明授权

US06472324B2 Method of manufacturing trench type element isolation structure 失效
标题翻译：制造沟槽型元件隔离结构的方法
公开(公告)号：US06472324B2
公开(公告)日：2002-10-29
申请号：US09809184
申请日：2001-03-16
申请人： Yoshihiko Kusakabe , Yasuki Morino
发明人： Yoshihiko Kusakabe , Yasuki Morino
IPC分类号： H01L21302
CPC分类号： H01L21/76224 , H01L21/31053 , H01L21/31612 , H01L21/31662
摘要： The present invention is directed to a method of manufacturing a trench type semiconductor element isolation structure including the steps of: (i) forming a silicon oxide film on a silicon substrate and forming a silicon nitride film on the silicon oxide film; (ii) forming a groove penetrating the silicon nitride film and the silicon oxide film, said groove reaching an interior of the silicon substrate; (iii) forming a thermal oxide film on an inner wall of said groove; (iv) depositing an oxide in said groove; (v) subjecting said oxide to a polishing treatment with the silicon nitride film used as a stopper layer, so that a part of the insulator is removed; (vi) etching the oxide by a predetermined amount of said oxide after completing the step (v); (vii) etching the silicon nitride film after completing the step (vi); and (viii) etching the silicon oxide film after completing the step (vii).
摘要翻译：本发明涉及一种制造沟槽型半导体元件隔离结构的方法，包括以下步骤：（i）在硅衬底上形成氧化硅膜并在氧化硅膜上形成氮化硅膜; （ii）形成贯穿所述氮化硅膜和所述氧化硅膜的槽，所述槽到达所述硅衬底的内部; （iii）在所述槽的内壁上形成热氧化膜; （iv）在所述槽中沉积氧化物; （v）对所述氧化物进行抛光处理，所述氮化硅膜用作阻挡层，从而去除绝缘体的一部分; （vi）在完成步骤（v）之后，用预定量的氧化物蚀刻氧化物; （vii）在完成步骤（vi）之后蚀刻氮化硅膜; 和（viii）在完成步骤（vii）之后蚀刻氧化硅膜。

8. 发明申请

US20120080757A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120080757A1
公开(公告)日：2012-04-05
申请号：US13376081
申请日：2009-06-05
申请人： Hisayuki Kato , Yoshihiko Kusakabe
发明人： Hisayuki Kato , Yoshihiko Kusakabe
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823468 , H01L21/823418 , H01L21/823814 , H01L21/823864 , H01L22/26 , H01L29/517 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： First protective films are formed to cover side surfaces of gate electrode portions. In an nMOS region, an extention implantation region is formed by causing a portion of the first protective film located on the side surface of the gate electrode portion to function as an offset spacer and using the offset spacer as a mask, and then, cleaning is done. Since silicon nitride films are formed on surfaces of the first protective films, the resistance to chemical solutions is improved. Furthermore, second protective films are formed on the first protective films, respectively. In a pMOS region, an extention implantation region is formed by causing a portion of the first protective film and a portion of the second protective film located on the side surface of the gate electrode portion to function as an offset spacer and using the offset spacer as the mask, and then, cleaning is done.
摘要翻译：形成第一保护膜以覆盖栅电极部分的侧表面。在nMOS区域中，通过使位于栅极电极部分的侧表面上的第一保护膜的一部分用作偏移间隔物并使用偏移间隔物作为掩模来形成延伸注入区域，然后清洁完成了由于在第一保护膜的表面上形成氮化硅膜，因此提高了对化学溶液的耐性。此外，在第一保护膜上分别形成第二保护膜。在pMOS区域中，通过使第一保护膜的一部分和位于栅极电极部分的侧表面上的第二保护膜的一部分用作偏移间隔物并使用偏移间隔物形成延伸注入区面具，然后进行清洁。

9. 发明授权

US07411834B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US07411834B2
公开(公告)日：2008-08-12
申请号：US11701404
申请日：2007-02-02
申请人： Yoshihiko Kusakabe , Kenichi Oto , Satoshi Kawasaki
发明人： Yoshihiko Kusakabe , Kenichi Oto , Satoshi Kawasaki
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C8/08 , G11C8/10 , G11C8/14 , G11C16/08
摘要： A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.

10. 发明授权

US5976260A Semiconductor producing apparatus, and wafer vacuum chucking device, gas cleaning method and nitride film forming method in semiconductor producing apparatus 失效
标题翻译：半导体制造装置，晶片真空夹紧装置，半导体制造装置中的气体净化方法和氮化物膜形成方法
公开(公告)号：US5976260A
公开(公告)日：1999-11-02
申请号：US612445
申请日：1996-03-07
申请人： Yoshimi Kinoshita , Tomoyuki Kanda , Katsuhisa Kitano , Kazuo Yoshida , Hiroshi Ohnishi , Kenichiro Yamanishi , Shigeo Sasaki , Hideki Komori , Taizo Eshima , Kouichirou Tsutahara , Toshihiko Noguchi , Toru Takahama , Yoshihiko Kusakabe , Takeshi Iwamoto , Nobuyuki Kosaka
发明人： Yoshimi Kinoshita , Tomoyuki Kanda , Katsuhisa Kitano , Kazuo Yoshida , Hiroshi Ohnishi , Kenichiro Yamanishi , Shigeo Sasaki , Hideki Komori , Taizo Eshima , Kouichirou Tsutahara , Toshihiko Noguchi , Toru Takahama , Yoshihiko Kusakabe , Takeshi Iwamoto , Nobuyuki Kosaka
IPC分类号： B23Q3/08 , B25B11/00 , C23C16/34 , C23C16/44 , C23C16/455 , C23C16/458 , C23C16/48 , H01L21/683 , C23C16/00
CPC分类号： C23C16/34 , B25B11/005 , C23C16/4405 , C23C16/455 , C23C16/4583 , C23C16/481 , H01L21/6838 , Y10T279/11
摘要： It is an object of the present invention to obtain a vacuum chucking which can vacuum suck a wafer even if dusts attach thereon. The main body of vacuum chuck (101) has a plurality of block grooves (125) on the surface on which the wafer (1) is sucked and fixed, in which vacuum evacuation paths (105) each for vacuum evacuating each block groove (125) are provided for each block groove (125). When the wafer (1) is sucked and fixed under low pressure, even if the degree of vacuum in one of the block grooves (125) decreases due to attachment of dusts on part of the suction surface, or the like, the wafer (1) can surely be sucked and held.
摘要翻译：本发明的目的是获得即使在其上附着有灰尘也能真空吸附晶片的真空吸盘。真空吸盘（101）的主体在其上吸引和固定晶片（1）的表面上具有多个块状凹槽（125），其中各真空抽空路径（105）用于真空抽吸每个块状凹槽（125））被设置用于每个块槽（125）。当晶片（1）在低压下被吸入和固定时，即使一个块状槽（125）中的一个真空度由于吸附表面的一部分上的灰尘等的附着而降低，晶片（1））肯定被吸住了。

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