专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5815462A Synchronous semiconductor memory device and synchronous memory module 失效
标题翻译：同步半导体存储器件和同步存储器模块
公开(公告)号：US5815462A
公开(公告)日：1998-09-29
申请号：US800905
申请日：1997-02-12
申请人： Yasuhiro Konishi , Hisashi Iwamoto , Takashi Araki , Yasumitsu Murai , Seiji Sawada
发明人： Yasuhiro Konishi , Hisashi Iwamoto , Takashi Araki , Yasumitsu Murai , Seiji Sawada
IPC分类号： G11C11/407 , G06F12/00 , G06F13/16 , G11C7/10 , G11C7/22 , G11C11/409 , G11C8/00
CPC分类号： G11C7/225 , G11C7/1039 , G11C7/1072 , G11C7/22
摘要： A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and thus clock access time and data hold time can be adjusted. Internal data read path is pipelined to include a first transfer gate responsive to the first clock signal for transferring internal read data and a second transfer gate responsive to the second clock signal for transferring the internal read data from the first transfer gate for external outputting through an output buffer. A synchronous semiconductor memory device is provided capable of setting clock access time and data hold time at the optimal values depending on the application and of reducing the clock access time.
摘要翻译：用于控制外部信号的输入和用于控制内部操作的第一时钟信号和用于控制数据输出的第二时钟信号分别被施加到分离的时钟输入节点。可以调整相对于第一时钟信号的数据输出定时，从而可以调整时钟存取时间和数据保持时间。内部数据读取路径被流水线化以包括响应于第一时钟信号的第一传送门，用于传送内部读取数据和第二传送门，响应于第二时钟信号，用于从第一传送门传送内部读取数据，以便通过输出缓冲区。提供一种同步半导体存储器件，其能够根据应用和减少时钟存取时间将时钟访问时间和数据保持时间设置在最佳值。

2. 发明授权

US5404338A Synchronous type semiconductor memory device operating in synchronization with an external clock signal 失效
标题翻译：与外部时钟信号同步工作的同步型半导体存储器件
公开(公告)号：US5404338A
公开(公告)日：1995-04-04
申请号：US189247
申请日：1994-01-31
申请人： Yasumitsu Murai , Hisashi Iwamoto , Yasuhiro Konishi , Naoya Watanabe , Seiji Sawada
发明人： Yasumitsu Murai , Hisashi Iwamoto , Yasuhiro Konishi , Naoya Watanabe , Seiji Sawada
IPC分类号： G11C11/407 , F02B75/02 , G11C7/10 , G11C11/401 , G11C11/409 , G11C13/00
CPC分类号： G11C7/222 , G11C7/1072 , F02B2075/027
摘要： In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.
摘要翻译：在同步半导体存储器件中，形成激活单元的存储器阵列（MA）被分成多个小存储器阵列（MK）。提供了两个小型存储器阵列的本地I / O线对（LIO）。跨字线的全局I / O线对（GIO）排列在字线分流区（WS）中。连接开关（BS）布置在本地I / O线对与全局I / O线对之间的交叉中。激活的存储器阵列中的每个小存储器阵列通过本地I / O线对连接到相应的全局I / O线对。从而，可以同时读取多个比特，而不增加互连占用的面积。使用读出放大器激活信号进行连接开关的控制。数据传输到为数据输出端子提供的读数据寄存器用于顺序数据输出或选择存储单元时，全局I / O线被预充电/均衡。外部时钟信号被分频以产生用于通过充电操作产生内部电压的相移内部时钟信号。

3. 发明授权

US5517462A Synchronous type semiconductor memory device operating in synchronization with an external clock signal 失效
公开(公告)号：US5517462A
公开(公告)日：1996-05-14
申请号：US381586
申请日：1995-01-31
申请人： Hisashi Iwamoto , Yasumitsu Murai , Yasuhiro Konishi , Naoya Watanabe , Seiji Sawada
发明人： Hisashi Iwamoto , Yasumitsu Murai , Yasuhiro Konishi , Naoya Watanabe , Seiji Sawada
IPC分类号： G11C11/407 , F02B75/02 , G11C7/10 , G11C11/401 , G11C11/409 , G11C13/00
CPC分类号： G11C7/222 , G11C7/1072 , F02B2075/027
摘要： In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.

4. 发明授权

US5592434A Synchronous semiconductor memory device 失效
标题翻译：同步半导体存储器件
公开(公告)号：US5592434A
公开(公告)日：1997-01-07
申请号：US548285
申请日：1995-10-25
申请人： Hisashi Iwamoto , Yasuhiro Konishi , Katsumi Dosaka , Yasumitsu Murai
发明人： Hisashi Iwamoto , Yasuhiro Konishi , Katsumi Dosaka , Yasumitsu Murai
IPC分类号： G11C11/409 , G11C7/10 , G11C11/401 , G11C11/407 , G11C7/00
CPC分类号： G11C7/1048 , G11C7/1072
摘要： To one memory array, global signal input/output line pairs in two systems, a switch for connecting the global IO line pairs to a write buffer group alternately on a clock cycle basis, and another switch for connecting the global IO line pairs to an equalize circuit alternately on a clock cycle basis are provided. During one clock cycle, writing of data through one global IO line pair and equalization of the other global IO line pair can be carried out in parallel. Therefore, data can be written easily at a high frequency.
摘要翻译：对于一个存储器阵列，两个系统中的全局信号输入/输出线对，用于以时钟周期交替地将全局IO线对连接到写缓冲器组的开关，以及用于将全局IO线对连接到等于提供了基于时钟周期的交替电路。在一个时钟周期内，可以并行执行通过一个全局IO线对写入数据和对另一个全局IO线对进行均衡。因此，可以高频地容易地写入数据。

5. 发明授权

US5796669A Synchronous semiconductor memory device 失效
标题翻译：同步半导体存储器件
公开(公告)号：US5796669A
公开(公告)日：1998-08-18
申请号：US900123
申请日：1997-07-25
申请人： Takashi Araki , Hisashi Iwamoto , Yasuhiro Konishi
发明人： Takashi Araki , Hisashi Iwamoto , Yasuhiro Konishi
IPC分类号： G11C11/407 , G11C11/406 , G11C7/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C7/1063
摘要： Switches (11, 12) select either of refresh address counters (6a, 6b) in accordance with a refresh bank set signal (.phi.REFADD) when a bank refresh signal (.phi.BANKREF) is activated. An internal bank address (int.BA) serves as the refresh bank set signal (.phi.REFADD) to control the switch (12) and the refresh address counter (6a or 6b) designated by the internal bank address (int.BA) performs a count operation in synchronization with a refresh clock (.phi.REFCLK). The switch (11) outputs either of refresh addresses (Ref.Add.sub.-- A , Ref.Add.sub.-- B ) which is updated. With this configuration provided is an SDRAM which allows access to data during a refresh operation.
摘要翻译：当bank刷新信号（phi BANKREF）被激活时，开关（11,12）根据刷新组设置信号（phi REFADD）来选择刷新地址计数器（6a，6b）。内部银行地址（int.BA）用作刷新组设置信号（phi REFADD）以控制开关（12），由内部银行地址（int.BA）指定的刷新地址计数器（6a或6b）执行计数操作与刷新时钟同步（phi REFCLK）。开关（11）输出更新的刷新地址（Ref.Add-A <0:10>，Ref.Add-B <0:10>）。提供这种配置是允许在刷新操作期间访问数据的SDRAM。

6. 发明授权

US5805603A Synchronous semiconductor memory device realizing high speed and accurate operation 失效
标题翻译：同步半导体存储器件实现高速和准确的操作
公开(公告)号：US5805603A
公开(公告)日：1998-09-08
申请号：US779068
申请日：1997-01-07
申请人： Takashi Araki , Yasuhiro Konishi , Hisashi Iwamoto
发明人： Takashi Araki , Yasuhiro Konishi , Hisashi Iwamoto
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/408 , G11C11/409 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1072
摘要： A synchronous semiconductor memory device is provided with a delay circuit between an input latch circuit and a pad. The synchronous semiconductor memory device can operate at a higher speed since respective external input signals supplied to a plurality of pads are delayed such that the time required for transmission from respective pads to the input latch circuit is equal, and that skew is eliminated.
摘要翻译：同步半导体存储器件在输入锁存电路和焊盘之间设置延迟电路。由于提供给多个焊盘的各个外部输入信号被延迟使得从各个焊盘传输到输入锁存电路所需的时间相等，同步半导体存储器件可以更高的速度工作，并且消除了偏斜。

7. 发明授权

US5530379A Output buffer circuit that can be shared by a plurality of interfaces and a semiconductor device using the same 失效
标题翻译：可以由多个接口共享的输出缓冲器电路和使用其的半导体器件
公开(公告)号：US5530379A
公开(公告)日：1996-06-25
申请号：US427186
申请日：1995-04-21
申请人： Yasuhiro Konishi , Takashi Araki , Hisashi Iwamoto
发明人： Yasuhiro Konishi , Takashi Araki , Hisashi Iwamoto
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/409 , H01L21/822 , H01L27/04 , H03K19/0175 , H03K19/0185 , H03K19/094
CPC分类号： G11C7/1051 , H03K19/018585
摘要： First and second transistors are connected via a first switch. Second and third transistors are connected in parallel via a second switch. Either an input signal or an output ground voltage is applied to the gate of a third transistor via a third switch. In a LVTTL version, the first switch is on and the second switch is off. By the third switch, the output ground voltage is applied to the gate of the third transistor. As a result, first and second, transistors are arranged in series between the output power supply voltage and the output ground voltage, resulting in an output buffer circuit corresponding to a LVTTL. In a GTL version, the first switch is off and the second switch is on. An input signal is applied to the gate of the third transistor by the third switch. As a result, second and third transistors are arranged in parallel to form an open drain. This can be used as an output buffer circuit corresponding to a GTL.
摘要翻译：第一和第二晶体管经由第一开关连接。第二和第三晶体管经由第二开关并联连接。输入信号或输出接地电压通过第三开关施加到第三晶体管的栅极。在LVTTL版本中，第一个开关打开，第二个开关关闭。通过第三开关，输出接地电压被施加到第三晶体管的栅极。结果，第一和第二晶体管串联布置在输出电源电压和输出接地电压之间，产生对应于LVTTL的输出缓冲电路。在GTL版本中，第一个开关关闭，第二个开关打开。输入信号通过第三开关施加到第三晶体管的栅极。结果，第二和第三晶体管平行布置以形成开漏。这可以用作对应于GTL的输出缓冲电路。

8. 发明授权

US6118730A Phase comparator with improved comparison precision and synchronous semiconductor memory device employing the same 失效
标题翻译：具有改进比较精度的相位比较器和采用该比较精度的同步半导体存储器件
公开(公告)号：US6118730A
公开(公告)日：2000-09-12
申请号：US295361
申请日：1999-04-21
申请人： Takashi Kubo , Yasumitsu Murai , Hisashi Iwamoto
发明人： Takashi Kubo , Yasumitsu Murai , Hisashi Iwamoto
IPC分类号： G11C11/407 , G11C7/22 , H03D13/00 , H03K5/26 , H03L7/00 , H03L7/081 , H03L7/089 , G11C8/00
CPC分类号： H03L7/089 , G11C7/22 , H03D13/004 , H03K5/26 , H03L7/0814
摘要： The phase comparator receives an output of a buffer receiving the first input signal and an output of a buffer receiving the second input signal, and outputs signals SLOW, FAST as a result of phase comparison. The phase comparator includes a waveform processing circuit for enlarging the phase difference between two input signals, and a comparison circuit for performing phase comparison based on the phase difference enlarged by the waveform processing circuit and outputting signals SLOW, FAST. Because of the function of the waveform processing circuit, the performance of the phase comparator can be improved significantly, without having to largely improve the performance of the comparison circuit.
摘要翻译：相位比较器接收接收第一输入信号的缓冲器的输出和接收第二输入信号的缓冲器的输出，并且作为相位比较的结果输出信号SLOW，FAST。相位比较器包括用于放大两个输入信号之间的相位差的波形处理电路和用于通过波形处理电路放大的相位差进行相位比较的比较电路，并输出信号SLOW，FAST。由于波形处理电路的功能，可以显着提高相位比较器的性能，而不必大幅提高比较电路的性能。

9. 发明授权

US5940344A Synchronous semiconductor memory device including internal clock signal generation circuit that generates an internal clock signal synchronizing in phase with external clock signal at high precision 失效
标题翻译：同步半导体存储器件包括内部时钟信号产生电路，其产生与外部时钟信号同步高精度的内部时钟信号
公开(公告)号：US5940344A
公开(公告)日：1999-08-17
申请号：US53058
申请日：1998-04-01
申请人： Yasumitsu Murai , Wataru Sakamoto , Hisashi Iwamoto
发明人： Yasumitsu Murai , Wataru Sakamoto , Hisashi Iwamoto
IPC分类号： G11C11/407 , G11C7/22 , G11C8/00
CPC分类号： G11C7/22
摘要： In an internal clock signal generation circuit, a phase comparator for detecting phase difference between an external clock signal and an internal clock signal includes a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the external clock signal is transmitted, and a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the internal clock signal is transmitted. The rising timing of the signal having a more lagging phase of the signals of the two signal lines becomes more gentle. As a result, the phase difference is increased, and the phase comparator can compare the phase at high precision.
摘要翻译：在内部时钟信号发生电路中，用于检测外部时钟信号和内部时钟信号之间的相位差的相位比较器包括相对于信号线的晶体管和电容器，通过该信号线发送对应于外部时钟信号的时钟信号以及相对于信号线的晶体管和电容器，通过该晶体管和电容器发送与内部时钟信号对应的时钟信号。具有两个信号线的信号的滞后相位的信号的上升定时变得更加平缓。结果，相位差增大，相位比较器可以高精度地比较相位。

10. 发明授权

US5946268A Internal clock signal generation circuit including delay line, and synchronous type semiconductor memory device including internal clock signal 失效
标题翻译：内部时钟信号发生电路包括延迟线，同步型半导体存储器件包括内部时钟信号
公开(公告)号：US5946268A
公开(公告)日：1999-08-31
申请号：US012558
申请日：1998-01-23
申请人： Hisashi Iwamoto , Yasumitsu Murai
发明人： Hisashi Iwamoto , Yasumitsu Murai
IPC分类号： G11C11/407 , G06F1/06 , G11C7/22 , G11C11/4076 , H03K5/00 , H03K5/13 , H03L7/00 , G11C7/00
CPC分类号： G11C7/22 , H03K5/133 , H03K2005/00071
摘要： An internal clock generation circuit includes a delay line in which a plurality of inverter circuits are connected in series. A switch and a capacitor are connected to an output node of each inverter circuit. The switch connected to each inverter circuit is turned on/off individually according to respective control signals. In response to the switch being turned on, the output node of a corresponding inverter circuit and the capacitor are connected, whereby the capacitance of the output node of the corresponding inverter circuit is altered. As a result, the transmission rate of the signal is altered.
摘要翻译：内部时钟生成电路包括多个逆变器电路串联连接的延迟线。开关和电容器连接到每个逆变器电路的输出节点。连接到每个逆变器电路的开关根据相应的控制信号单独打开/关闭。响应于开关导通，相应的逆变器电路的输出节点和电容器被连接，从而相应的逆变器电路的输出节点的电容被改变。结果，信号的传输速率被改变。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式