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1. 发明授权

US08076993B2 Balun circuit and integrated circuit device 有权
标题翻译：平衡电路和集成电路器件
公开(公告)号：US08076993B2
公开(公告)日：2011-12-13
申请号：US12529891
申请日：2008-03-11
申请人： Yasuhiro Hamada , Shuya Kishimoto , Kenichi Maruhashi , Masaharu Ito , Masahiro Tanomura , Naoyuki Orihashi
发明人： Yasuhiro Hamada , Shuya Kishimoto , Kenichi Maruhashi , Masaharu Ito , Masahiro Tanomura , Naoyuki Orihashi
IPC分类号： H03H7/42 , H01P3/08
CPC分类号： H01P5/10
摘要： A balun circuit comprising first through third CPW lines becoming signal I/O ports, a first differential transmission line for linking the central conductor of the second CPW line and the ground conductor of the first CPW line and for linking the ground conductor of the second CPW line and the central conductor of the first CPW line, a second differential transmission line for linking the central conductors of the first and third CPW lines and for linking the ground conductors of the first and third CPW lines, and a joint for connecting at least two ground conductors of the first through third CPW lines. The differential transmission line has a first line formed in a dielectric layer on a substrate, a second line arranged in the underlying layer, and an underlying line at a fixed potential arranged between the substrate and the second line.
摘要翻译：包括第一至第三CPW线变为信号I / O端口的平衡 - 不平衡转换电路，用于将第二CPW线的中心导体和第一CPW线的接地导体连接并用于连接第二CPW的接地导体的第一差分传输线线和第一CPW线的中心导体，用于连接第一和第三CPW线的中心导体并用于连接第一和第三CPW线的接地导体的第二差分传输线，以及用于连接至少两个第一至第三CPW线的接地导体。差分传输线具有形成在基板上的电介质层中的第一线，布置在下层中的第二线，以及布置在基板和第二线之间的固定电位的底线。

2. 发明授权

US08326244B2 Power amplifier, and method of controlling power amplifier 有权
标题翻译：功率放大器和功率放大器的控制方法
公开(公告)号：US08326244B2
公开(公告)日：2012-12-04
申请号：US12682175
申请日：2008-09-05
申请人： Kenichi Maruhashi , Masahiro Tanomura , Hidenori Shimawaki
发明人： Kenichi Maruhashi , Masahiro Tanomura , Hidenori Shimawaki
IPC分类号： H01Q11/12 , H04K3/00
CPC分类号： H03F1/56 , H03F1/0277 , H03F3/211 , H03F3/245 , H03F3/604 , H03F3/72 , H03F2200/15 , H03F2200/18 , H03F2200/222 , H03F2200/255 , H03F2200/387 , H03F2200/423 , H03F2203/21106 , H03F2203/21142 , H03F2203/21178 , H03F2203/7215 , H03F2203/7221 , H03F2203/7236
摘要： A power amplifier of the present invention comprises MOS transistor (1) having a gate length of 180 nm or less, and output matching circuit (5) connected to a drain terminal of MOS transistor (1). Also, MOS transistor (1) is applied with voltage Vd_n normalized by a voltage value allowable in a DC state as a drain-source voltage, where Vd_n is in a range of 0.5 to 0.9. ZL (=RH+j·XL) represents a value equal to a load impedance when viewing the output matching circuit (5) from the drain terminal normalized by gate width W (mm) of MOS transistor (1), and a real part (RL) of the ZL is RL>0.64×Vd_n+0.19 (Ω·mm), and RL
摘要翻译：本发明的功率放大器包括栅极长度为180nm以下的MOS晶体管（1）和与MOS晶体管（1）的漏极端子连接的输出匹配电路（5）。此外，向MOS晶体管（1）施加以直流状态允许的电压值归一化的电压Vd_n作为漏极 - 源极电压，其中Vd_n在0.5至0.9的范围内。 ZL（= RH + j·XL）表示当从由MOS晶体管（1）的栅极宽度W（mm）归一化的漏极端子观察输出匹配电路（5）时的负载阻抗等于实际部分（ RL）为RL> 0.64×Vd_n + 0.19（＆OHgr·mm），RL <0.64×Vd_n + 1.73（＆OHgr·mm）。

3. 发明申请

US20100225399A1 POWER AMPLIFIER, AND METHOD OF CONTROLLING POWER AMPLIFIER 有权
标题翻译：功率放大器和控制功率放大器的方法
公开(公告)号：US20100225399A1
公开(公告)日：2010-09-09
申请号：US12682175
申请日：2008-09-05
申请人： Kenichi Maruhashi , Masahiro Tanomura , Hidenori Shimawaki
发明人： Kenichi Maruhashi , Masahiro Tanomura , Hidenori Shimawaki
IPC分类号： H03F3/16
CPC分类号： H03F1/56 , H03F1/0277 , H03F3/211 , H03F3/245 , H03F3/604 , H03F3/72 , H03F2200/15 , H03F2200/18 , H03F2200/222 , H03F2200/255 , H03F2200/387 , H03F2200/423 , H03F2203/21106 , H03F2203/21142 , H03F2203/21178 , H03F2203/7215 , H03F2203/7221 , H03F2203/7236
摘要： A power amplifier of the present invention comprises MOS transistor (1) having a gate length of 180 nm or less, and output matching circuit (5) connected to a drain terminal of MOS transistor (1). Also, MOS transistor (1) is applied with voltage Vd_n normalized by a voltage value allowable in a DC state as a drain-source voltage, where Vd_n is in a range of 0.5 to 0.9. ZL (=RH+j·XL) represents a value equal to a load impedance when viewing the output matching circuit (5) from the drain terminal normalized by gate width W (mm) of MOS transistor (1), and a real part (RL) of the ZL is RL>0.64×Vd_n+0.19 (Ω· mm), and RL
摘要翻译：本发明的功率放大器包括栅极长度为180nm以下的MOS晶体管（1）和与MOS晶体管（1）的漏极端子连接的输出匹配电路（5）。此外，向MOS晶体管（1）施加以直流状态允许的电压值归一化的电压Vd_n作为漏极 - 源极电压，其中Vd_n在0.5至0.9的范围内。 ZL（= RH + j·XL）表示当从由MOS晶体管（1）的栅极宽度W（mm）归一化的漏极端子观察输出匹配电路（5）时的负载阻抗等于实际部分（ RL）为RL> 0.64×Vd_n + 0.19（＆OHgr·mm），RL <0.64×Vd_n + 1.73（＆OHgr·mm）。

4. 发明授权

US08630835B2 Simulation device, simulation method, and recording medium storing program 失效
标题翻译：仿真设备，仿真方法和记录介质存储程序
公开(公告)号：US08630835B2
公开(公告)日：2014-01-14
申请号：US13129341
申请日：2009-09-17
申请人： Masahiro Tanomura
发明人： Masahiro Tanomura
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Provided are a device model, a recording medium storing a program, a simulation circuit, device, and method that calculate a local temperature increase in an element. The device model according to the present invention is used for a semiconductor circuit simulation and has at least two model parameters. The model parameters include an electrical model describing temperature characteristics and a thermal model describing thermal characteristics and corresponding to the electrical model.
摘要翻译：提供了一种计算元件中的局部温度升高的装置型号，存储程序的记录介质，模拟电路，装置和方法。根据本发明的器件模型用于半导体电路仿真，并且具有至少两个模型参数。模型参数包括描述温度特性的电气模型和描述热特性并对应于电气模型的热模型。

5. 发明申请

US20100057412A1 CIRCUIT SIMULATOR, CIRCUIT SIMULATION METHOD AND PROGRAM 失效
标题翻译：电路仿真器，电路仿真方法和程序
公开(公告)号：US20100057412A1
公开(公告)日：2010-03-04
申请号：US12517258
申请日：2007-12-13
申请人： Masahiro Tanomura , Naotaka Kuroda , Masafumi Kawanaka
发明人： Masahiro Tanomura , Naotaka Kuroda , Masafumi Kawanaka
IPC分类号： G06G7/56 , G06F17/50 , G06G7/62 , G06F17/10
CPC分类号： G06F17/5036
摘要： Characteristics of a circuit element are predicted accurately by taking account not only of the temperature variation due to self-heating of the element but also of temperature variation due to heat transmission from an adjoining heater element. With reference to an electric network supplied from an electric network input unit (2) and a heat network supplied from a heat network input unit (3), a simulation unit (4) determines a first heat generation temperature resulting from the amount of self-heat generation of that element and a second heat generating temperature resulting from the amount of heat flowing into that element from other elements, respectively, for a plurality of elements which make up a semiconductor integrated circuit, calculates the element temperature of that element based on the first and second heat generation temperatures, and then calculates the voltage value and the current value in the element at that element temperature based on previously provided data indicative of temperature dependency of that element.
摘要翻译：通过考虑由于元件的自加热引起的温度变化以及由于邻接的加热器元件的热传递引起的温度变化，可以精确地预测电路元件的特性。参考从电网输入单元（2）提供的电网和从热网输入单元（3）提供的热网络，模拟单元（4）确定由自适应量产生的第一发热温度，对于构成半导体集成电路的多个元件，该元件的发热和由分别从其它元件流入该元件的热量产生的第二发热温度基于该元件的温度来计算元件温度第一和第二发热温度，然后基于先前提供的指示该元件的温度依赖性的数据计算该元件温度下的元件中的电压值和电流值。

6. 发明申请

US20090102563A1 Transimpedance amplifier 有权
标题翻译：互阻放大器
公开(公告)号：US20090102563A1
公开(公告)日：2009-04-23
申请号：US11990871
申请日：2006-07-24
申请人： Masahiro Tanomura , Kouji Matsunaga
发明人： Masahiro Tanomura , Kouji Matsunaga
IPC分类号： H03F1/34
CPC分类号： H03F1/42 , H03F1/08 , H03F1/34 , H03F2200/36
摘要： The present invention solves characteristic deterioration caused by peaking and a ground inductance, and provides a transimpedance amplifier capable of achieving a higher gain and a wider band. For this purpose, the transimpedance amplifier is configured to include a feedback circuit having two or more extreme frequencies and having a filter characteristic which is flat with respect to frequencies in a frequency region not more than a smallest extreme frequency among the extreme frequencies, which is flat with respect to frequencies in a frequency region not less than a largest extreme frequency among the extreme frequencies, and which has at least one negative inclination portion with respect to frequencies in a frequency region between the smallest and largest extreme frequencies.
摘要翻译：本发明解决了由峰值和接地电感引起的特性劣化，并且提供了能够实现更高增益和更宽带的跨阻放大器。为此，跨阻放大器被配置为包括具有两个或多个极端频率的反馈电路，并且具有相对于极端频率中不超过最小极端频率的频率区域中的频率为平坦的滤波器特性，其为相对于极端频率以上的最大极端频率以上的频率区域中的频率平坦，并且相对于最小和最大极端频率之间的频率区域中的频率具有至少一个负倾斜部分。

7. 发明授权

US09641027B2 Wireless power feeding system and wireless power feeding method 有权
公开(公告)号：US09641027B2
公开(公告)日：2017-05-02
申请号：US14345602
申请日：2012-05-25
申请人： Masayoshi Tsuji , Wataru Hattori , Masahiro Tanomura , Shuhei Yoshida
发明人： Masayoshi Tsuji , Wataru Hattori , Masahiro Tanomura , Shuhei Yoshida
IPC分类号： H01F37/00 , H02J17/00 , H02J5/00 , B60L11/18 , H01F38/14 , H02J7/02 , B60M7/00
CPC分类号： H02J50/12 , B60L11/182 , B60M7/00 , H01F38/14 , H02J5/005 , H02J7/025 , H02J17/00 , H02J50/05 , H02J50/50
摘要： A wireless power feeding system capable of long distance and highly efficient space transmission of power is provided. A wireless power feeding system includes a power transmitter, a power receiver, and a power receiving body. The power transmitter generates electromagnetic waves. The power receiver is supplied with power by means of the electromagnetic waves received from the power transmitter using a magnetic field resonance phenomenon. The power receiving body is inserted into an electromagnetic field created by the power transmitter and the power receiver, and receives power by means of the electromagnetic field.

8. 发明授权

US08063484B2 Semiconductor device and heat sink with 3-dimensional thermal conductivity 失效
标题翻译：具有三维导热性的半导体器件和散热片
公开(公告)号：US08063484B2
公开(公告)日：2011-11-22
申请号：US12311701
申请日：2007-10-25
申请人： Naotaka Kuroda , Akio Wakejima , Masahiro Tanomura , Hironobu Miyamoto
发明人： Naotaka Kuroda , Akio Wakejima , Masahiro Tanomura , Hironobu Miyamoto
IPC分类号： H01L23/495 , H01L23/10 , H01L23/34
CPC分类号： H01L23/367 , H01L23/373 , H01L23/66 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/072 , H01L2223/6644 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/49 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01031 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12041 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1423 , H01L2924/16195 , H01L2924/351 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device, comprising: a semiconductor element 20 having a rectangular two-dimensional geometry and serving as a heat source; and a heat sink section 25 having the semiconductor element 20 mounted thereon, wherein a relation among the directional components of said thermal conductivity is: Kzz≧Kyy>Kxx, where directional components of three-dimensional thermal conductivity of the heat sink section 25 in X, Y and Z directions are determined as Kxx, Kyy and Kzz, and where the longer side direction of the semiconductor element 20 is defined as X direction, the shorter side direction thereof is defined as Y direction and the thickness direction is defined as Z direction.
摘要翻译：一种半导体器件，包括：具有矩形二维几何形状并用作热源的半导体元件20; 以及其上安装有半导体元件20的散热部分25，其中所述热导率的方向分量之间的关系为：Kzz≥Kyy> Kxx，其中散热部分25的三维热导率的方向分量在X ，Y和Z方向被确定为Kxx，Kyy和Kzz，并且其中半导体元件20的长边方向被定义为X方向，其短边方向被定义为Y方向，并且厚度方向被定义为Z方向。

9. 发明申请

US20100007013A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20100007013A1
公开(公告)日：2010-01-14
申请号：US12311701
申请日：2007-10-25
申请人： Naotaka Kuroda , Akio Wakejima , Masahiro Tanomura , Hironobu Miyamoto
发明人： Naotaka Kuroda , Akio Wakejima , Masahiro Tanomura , Hironobu Miyamoto
IPC分类号： H01L23/34
CPC分类号： H01L23/367 , H01L23/373 , H01L23/66 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/072 , H01L2223/6644 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/49 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01031 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12041 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1423 , H01L2924/16195 , H01L2924/351 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device, comprising: a semiconductor element 20 having a rectangular two-dimensional geometry and serving as a heat source; and a heat sink section 25 having the semiconductor element 20 mounted thereon, wherein a relation among the directional components of said thermal conductivity is: Kzz≧Kyy>Kxx, where directional components of three-dimensional thermal conductivity of the heat sink section 25 in X, Y and Z directions are determined as Kxx, Kyy and Kzz, and where the longer side direction of the semiconductor element 20 is defined as X direction, the shorter side direction thereof is defined as Y direction and the thickness direction is defined as Z direction.
摘要翻译：一种半导体器件，包括：具有矩形二维几何形状并用作热源的半导体元件20; 以及其上安装有半导体元件20的散热部分25，其中所述热导率的方向分量之间的关系为：Kzz> = Kyy> Kxx，其中散热部分25的三维热导率的方向分量在 X，Y和Z方向被确定为Kxx，Kyy和Kzz，并且其中半导体元件20的长边方向被定义为X方向，其短边方向被定义为Y方向，并且厚度方向被定义为Z 方向。

10. 发明授权

US06924201B2 Heterojunction bipolar transistor and method of producing the same 有权
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US06924201B2
公开(公告)日：2005-08-02
申请号：US10447934
申请日：2003-05-29
申请人： Masahiro Tanomura , Hidenori Shimawaki , Yosuke Miyoshi , Fumio Harima
发明人： Masahiro Tanomura , Hidenori Shimawaki , Yosuke Miyoshi , Fumio Harima
IPC分类号： H01L29/73 , H01L21/308 , H01L21/331 , H01L29/205 , H01L29/737
CPC分类号： H01L29/66318 , H01L29/7371
摘要： A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.
摘要翻译：本发明的异质结双极晶体管由包括第一导电类型的基板和集电极层，第二导电类型的基极层和第一导电类型的发射极层的晶片制成，该晶体管在该基板上顺序层叠在基板上订购。首先，将晶片经由形成在发射极层上的预选位置上的第一光致抗蚀剂蚀刻到集电极层的预选深度，作为掩模。随后，用至少通过第一蚀刻步骤曝光的基底层和集电体层的侧壁蚀刻的集电极层和覆盖与用作掩模的侧壁相邻的集电极层的表面的一部分的第二光致抗蚀剂。

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