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1. 发明授权

US06924201B2 Heterojunction bipolar transistor and method of producing the same 有权
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US06924201B2
公开(公告)日：2005-08-02
申请号：US10447934
申请日：2003-05-29
申请人： Masahiro Tanomura , Hidenori Shimawaki , Yosuke Miyoshi , Fumio Harima
发明人： Masahiro Tanomura , Hidenori Shimawaki , Yosuke Miyoshi , Fumio Harima
IPC分类号： H01L29/73 , H01L21/308 , H01L21/331 , H01L29/205 , H01L29/737
CPC分类号： H01L29/66318 , H01L29/7371
摘要： A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.
摘要翻译：本发明的异质结双极晶体管由包括第一导电类型的基板和集电极层，第二导电类型的基极层和第一导电类型的发射极层的晶片制成，该晶体管在该基板上顺序层叠在基板上订购。首先，将晶片经由形成在发射极层上的预选位置上的第一光致抗蚀剂蚀刻到集电极层的预选深度，作为掩模。随后，用至少通过第一蚀刻步骤曝光的基底层和集电体层的侧壁蚀刻的集电极层和覆盖与用作掩模的侧壁相邻的集电极层的表面的一部分的第二光致抗蚀剂。

2. 发明授权

US06723664B2 Method and apparatus for depositing a thin film, and semiconductor device having a semiconductor-insulator junction 有权
标题翻译：用于沉积薄膜的方法和装置以及具有半导体 - 绝缘体结的半导体器件
公开(公告)号：US06723664B2
公开(公告)日：2004-04-20
申请号：US10041609
申请日：2002-01-10
申请人： Hideki Matsumura , Akira Izumi , Atsushi Masuda , Yasunobu Nashimoto , Yosuke Miyoshi , Shuji Nomura , Kazuo Sakurai , Shouichi Aoshima
发明人： Hideki Matsumura , Akira Izumi , Atsushi Masuda , Yasunobu Nashimoto , Yosuke Miyoshi , Shuji Nomura , Kazuo Sakurai , Shouichi Aoshima
IPC分类号： H01L2131
CPC分类号： C23C16/44 , C23C16/0236 , H01L21/28264 , H01L21/3185
摘要： This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV −1cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.
摘要翻译：本发明公开了一种方法和装置，其中在使用催化气相反应的薄膜沉积在基板上之前进行降低界面密度的预处理。催化气相反应是通过设置在基板表面附近的热催化体被提供给基板的处理气体产生的。在该预处理之后进行在基板表面上的薄膜沉积。热催化体由钨，钼，钽，钛或钒制成，并被加热器加热。并且，本发明还公开了一种具有半导体 - 绝缘体结的半导体器件，其界面密度为10 12 eV -1 cm -2以下，这是通过上述预处理在绝缘体中产生的薄膜沉积工艺。

3. 发明授权

US06717192B2 Schottky gate field effect transistor 有权
标题翻译：肖特基门场效应晶体管
公开(公告)号：US06717192B2
公开(公告)日：2004-04-06
申请号：US10337107
申请日：2003-01-06
申请人： Yosuke Miyoshi
发明人： Yosuke Miyoshi
IPC分类号： H01L2980
CPC分类号： H01L29/42316 , H01L29/812
摘要： A Schottky gate FET including a gate electrode having a gate extension, a drain electrode and a drain contact layer overlying a semi-insulating substrate, wherein the gate extension overlies at least part of the drain electrode and the drain contact layer. The vertical overlapping between the gate extension and the drain contact region prevents the current reduction to make the circuit module mounting the Schottky gate FET non-usable.
摘要翻译：一种肖特基栅极FET，包括具有栅极延伸的栅电极，覆盖半绝缘衬底的漏电极和漏极接触层，其中栅极延伸部至少覆盖漏电极和漏极接触层的一部分。栅极延伸和漏极接触区域之间的垂直重叠可防止电流降低，使得安装肖特基栅极FET的电路模块不可用。

4. 发明授权

US06325857B1 CVD apparatus 失效
标题翻译： CVD装置
公开(公告)号：US06325857B1
公开(公告)日：2001-12-04
申请号：US09434189
申请日：1999-11-04
申请人： Yosuke Miyoshi
发明人： Yosuke Miyoshi
IPC分类号： C23C1600
CPC分类号： C23C16/345 , C23C16/4401 , C23C16/4405 , C23C16/452
摘要： A CVD apparatus is provided, which is capable of cleaning the inside of a reaction chamber without affecting a catalyzer member after a CVD process is completed. This apparatus is comprised of a reaction chamber; a substrate stage located in the chamber, a substrate being placed on the stage; a catalyzer holder located in the chamber for holding a catalyzer member; the holder having an inner space in which the catalyzer member is fixed; the holder having an opening that communicates with the inner space and that faces toward the substrate placed on the stage; a shutter located in the chamber for closing the opening of the holder; a cleaning device for cleaning an inside of the chamber after a CVD process is completed; and a gas supply line for supplying a source gas into the inner space of the holder. When a film is formed on the substrate, the source gas is supplied into the inner space of the holder to generate an active species due to a catalysis of the catalyzer member, and the active species is supplied to the substrate placed on the stage through the opening of the holder. When the inside of the chamber is cleaned by the cleaning device, the substrate is taken out of the chamber and the opening of the holder is closed by the shutter, separating the catalyzer member located in the holder from an outside atmosphere of the holder.
摘要翻译：提供了一种CVD装置，其能够在CVD工艺完成之后清洁反应室的内部而不影响催化剂构件。该装置由反应室构成; 位于所述室中的衬底台，放置在所述台上的衬底; 位于所述室中用于保持催化剂构件的催化剂保持器; 所述保持器具有其中所述催化剂构件被固定的内部空间; 所述保持器具有与所述内部空间连通且面向放置在所述台架上的所述基板的开口; 位于所述室中的用于封闭所述保持器的开口的快门; 在CVD工艺完成之后用于清洁腔室内部的清洁装置; 以及用于将源气体供应到保持器的内部空间中的气体供应管线。当在基板上形成膜时，由于催化剂构件的催化，源气体被供应到保持器的内部空间以产生活性物质，并且活性物质通过持有人的开放。当通过清洁装置清洁室的内部时，将基板从室中取出并且保持器的开口被闸板封闭，将位于保持器中的催化剂构件与保持器的外部气氛分开。

5. 发明授权

US06462362B1 Heterojunction bipolar transistor having prevention layer between base and emitter 失效
标题翻译：异质结双极晶体管，其在基极和发射极之间具有预防层
公开(公告)号：US06462362B1
公开(公告)日：2002-10-08
申请号：US09711506
申请日：2000-11-14
申请人： Yosuke Miyoshi
发明人： Yosuke Miyoshi
IPC分类号： H01L21331
CPC分类号： H01L29/66318 , H01L29/7371
摘要： A bipolar transistor is disclosed, that comprises a collector layer of first conduction type, a base layer of second conduction type, formed on the collector layer, a prevention layer, formed on the base layer, for preventing carriers from being recombined, an emitter layer of first conduction type, formed on a first part of the prevention layer, and a base electrode, formed on a second part separated from the first part of the prevention layer.
摘要翻译：公开了一种双极晶体管，其包括形成在集电极层上的第一导电类型的集电极层，第二导电类型的基极层，形成在基极层上的用于防止载流子再结合的防止层，发射极层形成在防止层的第一部分上的第一导电类型和形成在与防止层的第一部分分离的第二部分上的基极。

6. 发明授权

US06225241B1 Catalytic deposition method for a semiconductor surface passivation film 失效
标题翻译：半导体表面钝化膜的催化沉积方法
公开(公告)号：US06225241B1
公开(公告)日：2001-05-01
申请号：US09007543
申请日：1998-01-15
申请人： Yosuke Miyoshi
发明人： Yosuke Miyoshi
IPC分类号： H01L2131
CPC分类号： H01L29/66318 , C23C16/345 , H01L21/3185
摘要： To provide a fabrication method of compound semiconductor devices which can improve the problems of conventional MESFETs, such as the breakdown voltage degradation owing to increase of the gate leak current or the electron traps in the passivation film, the drain current decrease because of the gate-lag, or the threshold voltage dispersion caused by the interfacial tension, and easily restrain the emitter-size effect of conventional mesa type HBT without revising or complicating its epitaxial layer structure, a fabrication method according to the invention of a semiconductor device having a high-resistance film (9) covering a part of a surface other than electrodes (5, 6, and 7) of the semiconductor device comprises a step of depositing the high-resistance film (9) by way of catalytic CVD. The fabrication method preferably further comprises a step of surface cleaning performed before the step of depositing for cleaning the surface of the semiconductor device by a gas including active hydrogen flowing on the surface. As for the high-resistance film, a material including no oxygen such as SiN is applied.
摘要翻译：为了提供化合物半导体器件的制造方法，其可以改善常规MESFET的问题，例如由于栅极泄漏电流的增加或钝化膜中的电子陷阱引起的击穿电压劣化，漏极电流由于栅极 - 滞后或由界面张力引起的阈值电压色散，并且容易抑制常规台面型HBT的发射极尺寸效应而不修改或使其外延层结构复杂化，根据本发明的具有高分辨率的半导体器件的半导体器件的制造方法，覆盖半导体器件的电极（5,6）和7以外的表面的一部分的电阻膜（9）包括通过催化CVD沉积高电阻膜（9）的步骤。制造方法优选还包括在通过包括在表面上流动的活性氢的气体进行沉积以清洁半导体器件的表面的步骤之前执行的表面清洁步骤。对于高电阻膜，施加不含氧的材料，例如SiN。

7. 发明授权

US06483135B1 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US06483135B1
公开(公告)日：2002-11-19
申请号：US09383983
申请日：1999-08-26
申请人： Masashi Mizuta , Masaaki Kuzuhara , Yasunobu Nashimoto , Kazunori Asano , Yosuke Miyoshi , Yasunori Mochizuki
发明人： Masashi Mizuta , Masaaki Kuzuhara , Yasunobu Nashimoto , Kazunori Asano , Yosuke Miyoshi , Yasunori Mochizuki
IPC分类号： H01L2980
CPC分类号： H01L29/402 , H01L29/42316 , H01L29/8128
摘要： A field effect transistor includes a semiconductor substrate with a channel layer being formed on its surface, a source electrode and a drain electrode formed at a distance on said semiconductor substrate, and a gate electrode placed between the source electrode and the drain electrode and making a Schottky junction with the channel layer. The gate electrode is provided with an overhanging field plate section and between the field plate section and the channel layer, there is laid a dielectric film. When the relative permittivity and the film thickness of the dielectric film are denoted by ∈ and t (nm), respectively, the following condition is satisfied 5≦∈
摘要翻译：场效应晶体管包括在其表面上形成有沟道层的半导体衬底，在所述半导体衬底上形成一定距离的源电极和漏电极，以及放置在源电极和漏极之间的栅电极，与通道层的肖特基结。栅电极设置有突出场板部分，并且在场板部分和沟道层之间设置介电膜。当介电膜的相对介电常数和膜厚分别表示为in和t（nm）时，满足以下条件5 <=在<8且100

8. 发明授权

US06349669B1 Method and apparatus for depositing a thin film, and semiconductor device having a semiconductor-insulator junction 失效
标题翻译：用于沉积薄膜的方法和装置以及具有半导体 - 绝缘体结的半导体器件
公开(公告)号：US06349669B1
公开(公告)日：2002-02-26
申请号：US09102665
申请日：1998-06-23
申请人： Hideki Matsumura , Akira Izumi , Atsushi Masuda , Yasunobu Nashimoto , Yosuke Miyoshi , Shuji Nomura , Kazuo Sakurai , Shouichi Aoshima
发明人： Hideki Matsumura , Akira Izumi , Atsushi Masuda , Yasunobu Nashimoto , Yosuke Miyoshi , Shuji Nomura , Kazuo Sakurai , Shouichi Aoshima
IPC分类号： C23C1600
CPC分类号： C23C16/44 , C23C16/0236 , H01L21/28264 , H01L21/3185
摘要： This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV−1 cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.
摘要翻译：本发明公开了一种方法和装置，其中在使用催化气相反应的薄膜沉积在基板上之前进行降低界面密度的预处理。催化气相反应是通过设置在基板表面附近的热催化体被提供给基板的处理气体产生的。在该预处理之后进行在基板表面上的薄膜沉积。热催化体由钨，钼，钽，钛或钒制成，并被加热器加热。而且，本发明还公开了一种具有半导体 - 绝缘体结的半导体器件，其界面电平密度为1012eV-1cm-2或更低，这是通过上述绝缘膜沉积工艺中的预处理而得到的。

9. 发明授权

US6100571A Fet having non-overlapping field control electrode between gate and drain 有权
标题翻译：在栅极和漏极之间具有不重叠的场控制电极
公开(公告)号：US6100571A
公开(公告)日：2000-08-08
申请号：US326702
申请日：1999-06-07
申请人： Masashi Mizuta , Masaaki Kuzuhara , Yasunobu Nashimoto , Kazunori Asano , Yosuke Miyoshi , Yasunori Mochizuki
发明人： Masashi Mizuta , Masaaki Kuzuhara , Yasunobu Nashimoto , Kazunori Asano , Yosuke Miyoshi , Yasunori Mochizuki
IPC分类号： H01L21/314 , H01L21/338 , H01L27/095 , H01L29/06 , H01L29/40 , H01L29/78 , H01L29/80 , H01L29/812
CPC分类号： H01L29/402 , H01L27/095 , H01L29/7813 , H01L29/812
摘要： A field control electrode 9 is formed over an insulating film 6 on a channel layer 2, between a gate electrode 5 and a drain electrode 8. Tantalum oxide (Ta.sub.2 O.sub.5), for example, may be used as the material for the insulating film 6.
摘要翻译：场控制电极9形成在沟道层2上的绝缘膜6之间，栅电极5和漏电极8之间。例如，可以使用氧化钽（Ta 2 O 5）作为绝缘膜6的材料。

10. 发明授权

US6069094A Method for depositing a thin film 失效
标题翻译：沉积薄膜的方法
公开(公告)号：US6069094A
公开(公告)日：2000-05-30
申请号：US924304
申请日：1997-09-05
申请人： Hideki Matsumura , Akira Izumi , Atsushi Masuda , Yasunobu Nashimoto , Yosuke Miyoshi , Shuji Nomura , Kazuo Sakurai , Shouichi Aoshima
发明人： Hideki Matsumura , Akira Izumi , Atsushi Masuda , Yasunobu Nashimoto , Yosuke Miyoshi , Shuji Nomura , Kazuo Sakurai , Shouichi Aoshima
IPC分类号： H01L21/205 , C23C16/02 , C23C16/44 , H01L21/28 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/318
CPC分类号： C23C16/44 , C23C16/0236 , H01L21/28264 , H01L21/3185
摘要： This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 10.sup.12 eV .sup.-1 cm.sup.-2 or less, which is brought by the above pre-treatment in the insulator film deposition process.
摘要翻译：本发明公开了一种方法和装置，其中在使用催化气相反应的薄膜沉积在基板上之前进行降低界面密度的预处理。催化气相反应是通过设置在基板表面附近的热催化体被提供给基板的处理气体产生的。在该预处理之后进行在基板表面上的薄膜沉积。热催化体由钨，钼，钽，钛或钒制成，并被加热器加热。并且，本发明还公开了一种具有半导体 - 绝缘体结的半导体器件，其界面电平密度为1012eV -1cm-2或更小，这是通过上述绝缘膜沉积工艺中的预处理所带来的。

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