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1. 发明授权

US6108793A Semiconductor device having timing-stabilization circuit and method of testing such semiconductor device 失效
标题翻译：具有时序稳定电路的半导体器件和测试这种半导体器件的方法
公开(公告)号：US6108793A
公开(公告)日：2000-08-22
申请号：US40288
申请日：1998-03-18
申请人： Yasuhiro Fujii , Hiroyoshi Tomita , Nobutaka Taniguchi , Yasurou Matsuzaki
发明人： Yasuhiro Fujii , Hiroyoshi Tomita , Nobutaka Taniguchi , Yasurou Matsuzaki
IPC分类号： G01R31/30 , G06F1/04 , H03L7/081 , H03L7/087 , H03L7/095
CPC分类号： H03L7/0805 , G01R31/3016 , G06F1/04 , H03L7/0814 , H03L7/087 , H03L7/095
摘要： A method of measuring a time which a timing-stabilization circuit requires in order to complete timing stabilization with regard to a semiconductor device provided with a first function to reset the timing-stabilization circuit and a second function to output a signal indicative of completion of the timing stabilization is disclosed. The method includes the steps of a) activating the timing-stabilization circuit, b) detecting a timing of the completion of the timing stabilization by using the second function, and c) measuring the time which the timing-stabilization circuit requires to complete the timing stabilization based on the timing.
摘要翻译：一种测量定时稳定电路所需的时间的方法，以便对具有第一功能的半导体器件完成定时稳定以复位定时稳定电路，以及第二功能，以输出指示完成的信号公开了定时稳定。该方法包括以下步骤：a）激活定时稳定电路，b）通过使用第二功能来检测定时稳定的定时，以及c）测量定时稳定电路完成定时所需的时间基于时间稳定。

2. 发明授权

US06194932B1 Integrated circuit device 有权
标题翻译：集成电路器件
公开(公告)号：US06194932B1
公开(公告)日：2001-02-27
申请号：US09383015
申请日：1999-08-25
申请人： Yoshihiro Takemae , Yasurou Matsuzaki , Hiroyoshi Tomita , Nobutaka Taniguchi
发明人： Yoshihiro Takemae , Yasurou Matsuzaki , Hiroyoshi Tomita , Nobutaka Taniguchi
IPC分类号： H03L700
CPC分类号： G11C7/222 , G06F1/10 , G11C7/22 , H03L7/0814
摘要： The present invention omits a variable delay circuit (10 in FIG. 1) inside a DLL circuit, and instead, creates a timing synchronization circuit, which generates a second reference clock. The timing synchronization circuit shifts the phase of a first reference clock generated by a frequency divider to the timing of a timing signal generated from the other variable delay circuit so that the second reference clock matches to the timing signal. Then, a phase comparator compares the divided first reference clock to a variable clock that delays the second reference clock, and controls the delay time of the variable delay circuit so that both clocks are in phase. As a result, one variable delay circuit can be omitted, and a DLL circuit that uses a divided clock can be configured.
摘要翻译：本发明省略了DLL电路内部的可变延迟电路（图1中的10），而是产生产生第二参考时钟的定时同步电路。定时同步电路将由分频器产生的第一参考时钟的相位移位到从另一个可变延迟电路产生的定时信号的定时，使得第二参考时钟与定时信号相匹配。然后，相位比较器将分频的第一参考时钟与延迟第二参考时钟的可变时钟进行比较，并且控制可变延迟电路的延迟时间，使得两个时钟同相。结果，可以省略一个可变延迟电路，并且可以配置使用分频时钟的DLL电路。

3. 发明授权

US06181174B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06181174B2
公开(公告)日：2001-01-30
申请号：US09404221
申请日：1999-09-23
申请人： Waichirou Fujieda , Yasuharu Sato , Nobutaka Taniguchi , Hiroyoshi Tomita , Yasurou Matsuzaki
发明人： Waichirou Fujieda , Yasuharu Sato , Nobutaka Taniguchi , Hiroyoshi Tomita , Yasurou Matsuzaki
IPC分类号： H03L706
CPC分类号： H03L7/0805 , G06F1/08 , G06F1/10 , G11C7/1039 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , H03K5/133 , H03K23/58 , H03L7/0814
摘要： A semiconductor integrated circuit device includes a DLL circuit. The DLL circuit includes a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock. A delay system includes a variable delay circuit which delays the dummy clock. A control circuit controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.
摘要翻译：半导体集成电路装置包括DLL电路。 DLL电路包括分频器，该分频器以分频比对输入时钟进行分频，该分频比根据输入时钟的频率而变化，从而产生虚拟时钟和参考时钟。延迟系统包括延迟虚拟时钟的可变延迟电路。控制电路控制可变延迟电路的延迟量，使得来自延迟系统和参考时钟的延迟的虚拟时钟的相位变为零。

4. 发明授权

US6063640A Semiconductor wafer testing method with probe pin contact 失效
标题翻译：半导体晶圆测试方法与探针接触
公开(公告)号：US6063640A
公开(公告)日：2000-05-16
申请号：US30349
申请日：1998-02-25
申请人： Masataka Mizukoshi , Hidehiko Akasaki , Masao Nakano , Yasuhiro Fujii , Shinnosuke Kamata , Makoto Yanagisawa , Yasurou Matsuzaki , Toyonobu Yamada , Masami Matsuoka , Hiroyoshi Tomita
发明人： Masataka Mizukoshi , Hidehiko Akasaki , Masao Nakano , Yasuhiro Fujii , Shinnosuke Kamata , Makoto Yanagisawa , Yasurou Matsuzaki , Toyonobu Yamada , Masami Matsuoka , Hiroyoshi Tomita
IPC分类号： H01L23/58 , G01R31/26 , H01L21/66
CPC分类号： H01L22/32 , H01L22/22 , H01L2224/05554 , Y10S438/977
摘要： A semiconductor wafer testing method includes a pre-test step for forming a temporary test film on a surface of a semiconductor wafer, a test step for testing the semiconductor wafer by applying a probe to the temporary test film and a post-test step for exfoliating the temporary test film from the surface of the semiconductor wafer. The temporary test film includes test electrode groups each provided with a plurality of regularly arranged test electrodes, and wiring patterns for electrically connecting the test electrodes with corresponding ones of semiconductor unit electrodes in respective semiconductor units on the semiconductor wafer. Probe pins of said probe are arranged so as to be aligned with corresponding ones of the test electrodes of the respective test electrode groups.
摘要翻译：半导体晶片测试方法包括：在半导体晶片的表面上形成临时测试膜的预测试步骤，通过向临时测试膜施加探针来测试半导体晶片的测试步骤和用于去角质的后测试步骤来自半导体晶片表面的临时测试膜。临时测试膜包括各自设置有多个规则排列的测试电极的测试电极组和用于将测试电极与半导体晶片上的各个半导体单元中的相应半导体单元电极电连接的布线图案。所述探针的探头针布置成与各个测试电极组的相应测试电极对齐。

5. 发明授权

US06907555B1 Self-test circuit and memory device incorporating it 有权
标题翻译：自检电路和结合其的存储器件
公开(公告)号：US06907555B1
公开(公告)日：2005-06-14
申请号：US09691115
申请日：2000-10-19
申请人： Yukihiro Nomura , Hiroyuki Fujimoto , Takahiro Suzuki , Tatsuya Kanda , Yasurou Matsuzaki , Masahiko Saitou , Hiroyoshi Tomita
发明人： Yukihiro Nomura , Hiroyuki Fujimoto , Takahiro Suzuki , Tatsuya Kanda , Yasurou Matsuzaki , Masahiko Saitou , Hiroyoshi Tomita
IPC分类号： G01R31/28 , G01R31/3185 , G06F12/16 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , G11C29/12 , G11C29/44
CPC分类号： G11C29/44
摘要： The present invention is a self-test circuit (BIST) incorporated in the memory device, which is activated in response to a test activation signal from outside. When this self-test circuit is activated in response to a test activation signal (WBIZ) from outside, it generates a test operation command (WBI-CMD), generates a test address (WBI-ADD), and generates test data (WBI-DATA). Furthermore, after the self-test circuit writes the test data to a memory cell, it effects a comparison to establish whether or not the read data that is read from this memory cell is the same as the test data that was written thereto and stores information as to the result of this comparison. This comparison result information is then output to the outside.
摘要翻译：本发明是一种结合在存储器件中的自检电路（BIST），其响应于来自外部的测试激活信号被激活。当该自检电路响应于来自外部的测试激活信号（WBIZ）被激活时，它产生测试操作命令（WBI-CMD），生成测试地址（WBI-ADD），并生成测试数据（WBI- 数据）。此外，在自检电路将测试数据写入存储单元之后，进行比较以确定从该存储单元读取的读取数据是否与写入的测试数据相同并存储信息关于这个比较的结果。然后将该比较结果信息输出到外部。

6. 发明授权

US06333660B2 Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权
公开(公告)号：US06333660B2
公开(公告)日：2001-12-25
申请号：US09780475
申请日：2001-02-12
申请人： Masao Taguchi , Hiroyoshi Tomita , Yasurou Matsuzaki
发明人： Masao Taguchi , Hiroyoshi Tomita , Yasurou Matsuzaki
IPC分类号： H03K3013
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

7. 发明授权

US6154405A Semiconductor memory device having a dummy cell resetting the bit lines to a reset potential that is based on data read in a previous read data 失效
标题翻译：具有虚设单元的半导体存储器件，其将位线复位为基于在先前读取数据中读取的数据的复位电位
公开(公告)号：US6154405A
公开(公告)日：2000-11-28
申请号：US924315
申请日：1997-09-05
申请人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Hirohiko Mochizuki , Hiroyoshi Tomita , Yasurou Matsuzaki , Tadao Aikawa
发明人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Hirohiko Mochizuki , Hiroyoshi Tomita , Yasurou Matsuzaki , Tadao Aikawa
IPC分类号： G11C11/409 , G11C7/10 , G11C7/12 , G11C11/401 , G11C11/407 , G11C11/4096 , G11C7/02
CPC分类号： G11C11/4096 , G11C7/1048 , G11C7/12
摘要： A semiconductor memory device includes memory cells, word lines connected to the memory cells, bit lines connected to the memory cells, and a first circuit which resets the bit lines to a reset potential which is based on data read in a previous read cycle.
摘要翻译：半导体存储器件包括存储器单元，连接到存储器单元的字线，连接到存储器单元的位线，以及基于在先前读取周期中读取的数据将位线复位到复位电位的第一电路。

8. 发明授权

US6151274A System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor 有权
标题翻译：由同步半导体器件构成的系统，用于调整每个输入端和用于其的半导体器件的时序
公开(公告)号：US6151274A
公开(公告)日：2000-11-21
申请号：US440665
申请日：1999-11-16
申请人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima
发明人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima
IPC分类号： G06F13/42 , G06F1/10 , G06F1/12 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/4093 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/00 , H03L7/081 , H04L7/00 , G11C8/00
CPC分类号： H03L7/0805 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/133 , H03K5/135 , H03L7/00 , H03L7/0814 , G11C2207/108
摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.
摘要翻译：公开了一种用于实现这种系统的系统和半导体器件。该系统至少使用半导体器件来与外部时钟产生的内部时钟同步地检索输入信号，该输入信号与外部时钟同步地保持有效。即使在时钟与接收端的信号之间产生相位差的情况下，或者即使在时钟输入电路与接收端的半导体装置中的其他信号输入电路之间产生相位差的情况下，数据可以高速转移。在接收端的半导体器件的每个输入电路包括输入定时调整电路，用于调节施加到输入电路的时钟的相位，使得输入电路以有效和稳定的状态检索输入信号。在输入信号与输入信号和时钟之间的偏差相比较小的情况下，输入定时调整电路被多个输入电路共享。

9. 发明授权

US6028816A System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor 失效
公开(公告)号：US6028816A
公开(公告)日：2000-02-22
申请号：US924705
申请日：1997-09-05
申请人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima , Masao Nakano
发明人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima , Masao Nakano
IPC分类号： G06F13/42 , G06F1/10 , G06F1/12 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/4093 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/00 , H03L7/081 , H04L7/00 , G11C8/00
CPC分类号： H03L7/0805 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/133 , H03K5/135 , H03L7/00 , H03L7/0814 , G11C2207/108
摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.

10. 发明授权

US06205082B1 LSI device with memory and logics mounted thereon 有权
标题翻译：具有安装在其上的存储器和逻辑的LSI器件
公开(公告)号：US06205082B1
公开(公告)日：2001-03-20
申请号：US09304589
申请日：1999-05-04
申请人： Hiroyoshi Tomita , Yasurou Matsuzaki , Masao Taguchi
发明人： Hiroyoshi Tomita , Yasurou Matsuzaki , Masao Taguchi
IPC分类号： G11C800
CPC分类号： G11C7/1084 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C2207/105 , G11C2207/108 , H01L24/45 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/49175 , H01L2924/00014 , H01L2924/00
摘要： A data signal is output from an output circuit of a first chip and sent to a data input terminal in the second chip via a data lead line based on an output clock in first chip, which is sent to the second chip. And an input circuit in a second chip receives the data signal and transfers it inside in response to a transfer clock that has been generated from the output clock in the first chip. In synchronism with a single reference clock in the first chip, therefore, a data signal can be transferred to the second chip from the first chip at a high speed.
摘要翻译：数据信号从第一芯片的输出电路输出，并经由数据引线，基于第一芯片中的输出时钟发送到第二芯片中的数据输入端子，该输出时钟发送到第二芯片。并且第二芯片中的输入电路响应于从第一芯片中的输出时钟产生的传输时钟，接收数据信号并将其传送到内部。因此，与第一芯片中的单个参考时钟同步，数据信号可以从第一芯片高速传输到第二芯片。

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