专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6028816A System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor 失效
公开(公告)号：US6028816A
公开(公告)日：2000-02-22
申请号：US924705
申请日：1997-09-05
申请人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima , Masao Nakano
发明人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima , Masao Nakano
IPC分类号： G06F13/42 , G06F1/10 , G06F1/12 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/4093 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/00 , H03L7/081 , H04L7/00 , G11C8/00
CPC分类号： H03L7/0805 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/133 , H03K5/135 , H03L7/00 , H03L7/0814 , G11C2207/108
摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.

2. 发明授权

US6151274A System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor 有权
标题翻译：由同步半导体器件构成的系统，用于调整每个输入端和用于其的半导体器件的时序
公开(公告)号：US6151274A
公开(公告)日：2000-11-21
申请号：US440665
申请日：1999-11-16
申请人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima
发明人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima
IPC分类号： G06F13/42 , G06F1/10 , G06F1/12 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/4093 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/00 , H03L7/081 , H04L7/00 , G11C8/00
CPC分类号： H03L7/0805 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/133 , H03K5/135 , H03L7/00 , H03L7/0814 , G11C2207/108
摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.
摘要翻译：公开了一种用于实现这种系统的系统和半导体器件。该系统至少使用半导体器件来与外部时钟产生的内部时钟同步地检索输入信号，该输入信号与外部时钟同步地保持有效。即使在时钟与接收端的信号之间产生相位差的情况下，或者即使在时钟输入电路与接收端的半导体装置中的其他信号输入电路之间产生相位差的情况下，数据可以高速转移。在接收端的半导体器件的每个输入电路包括输入定时调整电路，用于调节施加到输入电路的时钟的相位，使得输入电路以有效和稳定的状态检索输入信号。在输入信号与输入信号和时钟之间的偏差相比较小的情况下，输入定时调整电路被多个输入电路共享。

3. 发明授权

US6078514A Semiconductor device and semiconductor system for high-speed data transfer 失效
标题翻译：半导体器件和半导体系统，用于高速数据传输
公开(公告)号：US6078514A
公开(公告)日：2000-06-20
申请号：US61023
申请日：1998-04-16
申请人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
发明人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
IPC分类号： G11C11/41 , G11C7/10 , G11C7/22 , G11C11/401 , H01L21/60 , H01L25/00 , H01L27/10 , H01L25/04 , H01L23/36
CPC分类号： H01L23/60 , G11C7/1006 , G11C7/22 , H01L24/49 , H01L25/0655 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L24/48 , H01L27/0266 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/1305 , H01L2924/13091 , H01L2924/30105
摘要： A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.
摘要翻译：半导体系统包括至少一个逻辑芯片和布置成使得至少一个存储器芯片的一侧面向至少一个逻辑芯片的一侧的至少一个存储器芯片。所述半导体系统还包括为所述至少一个逻辑芯片提供的用于与相邻存储器芯片进行数据传输的第一输入/输出节点，为所述至少一个存储器芯片提供的第二输入/输出节点，用于与相邻的逻辑芯片以及容纳所述至少一个逻辑芯片和所述至少一个存储器芯片的封装，其中所述第一输入/输出节点沿着所述至少一个逻辑芯片的一侧布置，并且所述第二输入/输出节点是沿着至少一个存储器芯片的一侧布置。

4. 发明授权

US5767712A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5767712A
公开(公告)日：1998-06-16
申请号：US892066
申请日：1997-07-14
申请人： Yoshihiro Takemae , Masao Taguchi , Yukinori Kodama , Makoto Yanagisawa , Takaaki Suzuki , Junji Ogawa , Atsushi Hatakeyama , Hirohiko Mochizuki , Hideaki Kawai
发明人： Yoshihiro Takemae , Masao Taguchi , Yukinori Kodama , Makoto Yanagisawa , Takaaki Suzuki , Junji Ogawa , Atsushi Hatakeyama , Hirohiko Mochizuki , Hideaki Kawai
IPC分类号： G06F1/04 , G11C7/22 , H01L27/02 , H03K3/356 , H03K5/13 , H03K5/1534 , H03K5/24 , H03L7/00
CPC分类号： G06F1/04 , G11C7/22 , G11C7/222 , H03K3/356113 , H03K3/356156 , H03K5/133 , H03K5/1534 , H03K5/249
摘要： A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.
摘要翻译：一种半导体器件包括：单脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟信号的周期时间根据来自单触发脉冲发生电路的单触发脉冲输出，内部时钟发生电路，其基于由循环时间测量电路测量的周期时间和从单次脉冲发生电路输出的单次脉冲产生第二时钟信号; 射击脉冲发生电路。第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟的周期时间获得特定时间信号，以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。

5. 发明授权

US06166992A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06166992A
公开(公告)日：2000-12-26
申请号：US517338
申请日：2000-03-02
申请人： Yoshihiro Takemae , Masao Taguchi , Yukinori Kodama , Makoto Yanagisawa , Takaaki Suzuki , Junji Ogawa , Atsushi Hatakeyama , Hirohiko Mochizuki , Hideaki Kawai
发明人： Yoshihiro Takemae , Masao Taguchi , Yukinori Kodama , Makoto Yanagisawa , Takaaki Suzuki , Junji Ogawa , Atsushi Hatakeyama , Hirohiko Mochizuki , Hideaki Kawai
IPC分类号： G06F1/04 , G11C7/22 , H01L27/02 , H03K3/356 , H03K5/13 , H03K5/1534 , H03K5/24 , G11C8/00
CPC分类号： G06F1/04 , G11C7/22 , G11C7/222 , H03K3/356113 , H03K3/356156 , H03K5/133 , H03K5/1534 , H03K5/249
摘要： A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle-time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.
摘要翻译：一种半导体器件包括：单触发脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟的周期时间来自单触发脉冲发生电路输出的单触发脉冲的信号;内部时钟发生电路，其基于由周期时间测量电路测量的周期时间和从一个脉冲发生电路输出的单次脉冲产生第二时钟信号 -shot脉冲发生电路。第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟信号的周期时间来获得特定时间时钟信号;以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。

6. 发明授权

US6009039A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US6009039A
公开(公告)日：1999-12-28
申请号：US14976
申请日：1998-01-28
申请人： Yoshihiro Takemae , Masao Taguchi , Yukinori Kodama , Makoto Yanagisawa , Takaaki Suzuki , Junji Ogawa , Atsushi Hatakeyama , Hirohiko Mochizuki , Hideaki Kawai
发明人： Yoshihiro Takemae , Masao Taguchi , Yukinori Kodama , Makoto Yanagisawa , Takaaki Suzuki , Junji Ogawa , Atsushi Hatakeyama , Hirohiko Mochizuki , Hideaki Kawai
IPC分类号： G06F1/04 , G11C7/22 , H03K3/356 , H03K5/13 , H03K5/1534 , H03K5/24 , G11C8/00 , G11C16/04
CPC分类号： G11C7/222 , G06F1/04 , G11C7/22 , H03K3/356113 , H03K3/356156 , H03K5/133 , H03K5/1534 , H03K5/249 , G11C7/04
摘要： A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.
摘要翻译：一种半导体器件包括：单脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟信号的周期时间根据来自单触发脉冲发生电路的单触发脉冲输出，内部时钟发生电路，其基于由循环时间测量电路测量的周期时间和从单次脉冲发生电路输出的单次脉冲产生第二时钟信号; 射击脉冲发生电路。第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟信号的周期时间来获得特定时间时钟信号;以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。

7. 发明授权

US06774655B2 Semiconductor device, method of testing the semiconductor device, and semiconductor integrated circuit 有权
标题翻译：半导体器件，半导体器件的测试方法以及半导体集成电路
公开(公告)号：US06774655B2
公开(公告)日：2004-08-10
申请号：US10622472
申请日：2003-07-21
申请人： Yasurou Matsuzaki , Masao Nakano , Toshiya Uchida , Atsushi Hatakeyama , Kenichi Kawasaki , Yasuhiro Fujii
发明人： Yasurou Matsuzaki , Masao Nakano , Toshiya Uchida , Atsushi Hatakeyama , Kenichi Kawasaki , Yasuhiro Fujii
IPC分类号： G01R3102
CPC分类号： G11C29/022 , G11C29/02
摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.
摘要翻译：公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

8. 发明授权

US06621283B1 Semiconductor device, method of testing the semiconductor device, and semiconductor integrated circuit 有权
标题翻译：半导体器件，半导体器件的测试方法以及半导体集成电路
公开(公告)号：US06621283B1
公开(公告)日：2003-09-16
申请号：US09437221
申请日：1999-11-10
申请人： Yasurou Matsuzaki , Masao Nakano , Toshiya Uchida , Atsushi Hatakeyama , Kenichi Kawasaki , Yasuhiro Fujii
发明人： Yasurou Matsuzaki , Masao Nakano , Toshiya Uchida , Atsushi Hatakeyama , Kenichi Kawasaki , Yasuhiro Fujii
IPC分类号： G01R3102
CPC分类号： G11C29/022 , G11C29/02
摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.
摘要翻译：公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

9. 发明授权

US5978884A Semiconductor memory device having a single line data bus and latch circuits for improved pipeline operations 失效
标题翻译：半导体存储器件具有单线数据总线和用于改进管线操作的锁存电路
公开(公告)号：US5978884A
公开(公告)日：1999-11-02
申请号：US880890
申请日：1997-06-23
申请人： Shusaku Yamaguchi , Atsushi Hatakeyama , Masato Takita , Tadao Aikawa , Hirohiko Mochizuki
发明人： Shusaku Yamaguchi , Atsushi Hatakeyama , Masato Takita , Tadao Aikawa , Hirohiko Mochizuki
IPC分类号： G11C11/413 , G11C7/10 , G11C11/407 , G11C11/409 , G11C19/00 , G11C19/28 , G06F13/00 , G11C7/00
CPC分类号： G11C7/1048 , G11C19/00 , G11C19/28 , G11C7/1039
摘要： A semiconductor memory device uses a wave pipeline system which can reduce a power consumption by reducing a current for charging a data bus between a memory core part and an output circuit. A single line data bus transmits read data output from the memory core part. A data bus drive circuit outputs the read read data to send to the single data bus. Each of a plurality of data latch circuits has a data input terminal connected to the data bus. A data input control circuit inputs the read data which is serially transmitted on the data bus to the data latch circuits in parallel in response to an operation of the data bus drive circuit. A data output control circuit outputs the latched read data in an order of latching by sequentially selecting outputs of the data latch circuits.
摘要翻译：半导体存储器件使用波浪管线系统，其可以通过减少用于对存储器核心部分和输出电路之间的数据总线充电的电流来降低功耗。单行数据总线发送从存储器核心部分输出的读取数据。数据总线驱动电路输出读取的数据以发送到单个数据总线。多个数据锁存电路中的每一个具有连接到数据总线的数据输入端子。数据输入控制电路响应于数据总线驱动电路的操作，将数据总线上串行发送的读取数据并行输入数据锁存电路。数据输出控制电路通过依次选择数据锁存电路的输出来以锁存顺序输出锁存的读取数据。

10. 发明授权

US5889725A Decoder circuit for a semiconductor memory device 失效
标题翻译：一种用于半导体存储器件的解码器电路
公开(公告)号：US5889725A
公开(公告)日：1999-03-30
申请号：US915332
申请日：1997-08-20
申请人： Tadao Aikawa , Hirohiko Mochizuki , Atsushi Hatakeyama , Shusaku Yamaguchi , Koichi Nishimura
发明人： Tadao Aikawa , Hirohiko Mochizuki , Atsushi Hatakeyama , Shusaku Yamaguchi , Koichi Nishimura
IPC分类号： G11C11/413 , G11C8/10 , G11C8/00
CPC分类号： G11C8/10
摘要： A semiconductor or memory device has a decoder circuit for decoding a plurality of external address signals. The external address signals include first and second external address signals. A first address buffer receives the first external address signals and outputs first internal address signals to first address lines. A second address buffer receives the second external address signals and outputs second internal address signals to second address lines. First predecoders have input terminals connected to the first address lines, and output first predecode signals to first predecode lines. Second predecoders have input terminals connected to the second address lines and output second predecode signals to second predecode lines. Main decoders have input terminals connected to the first predecode lines and the second predecode lines and output decode signals. The number of the first external address signals are greater than the number of the second external address signals. The second predecoders and the second predecode lines are provided at least in double in such a manner that inputs of the main decoders to be connected to each of the second predecode lines are equal in number to inputs of the main decoders to be connected to each of the first predecode lines. It is possible to shorten the transition time of predecode signals because of the same capacitive load of the predecoder circuit.
摘要翻译：半导体或存储器件具有用于解码多个外部地址信号的解码器电路。外部地址信号包括第一和第二外部地址信号。第一地址缓冲器接收第一外部地址信号，并将第一内部地址信号输出到第一地址线。第二地址缓冲器接收第二外部地址信号，并将第二内部地址信号输出到第二地址线。第一预解码器具有连接到第一地址线的输入端，并将第一预解码信号输出到第一预解码线。第二预解码器具有连接到第二地址线的输入端，并将第二预解码信号输出到第二预解码线。主解码器具有连接到第一预解码线和第二预解码线并输出解码信号的输入端。第一外部地址信号的数量大于第二外部地址信号的数量。第二预解码器和第二预解码线以至少两个方式提供，使得要连接到每个第二预解码线的主解码器的输入数量等于要连接到每个的主解码器的输入第一个预先代码行。由于预解码器电路的容性负载相同，可以缩短预解码信号的转换时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式