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1. 发明授权

US06333660B2 Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权
公开(公告)号：US06333660B2
公开(公告)日：2001-12-25
申请号：US09780475
申请日：2001-02-12
申请人： Masao Taguchi , Hiroyoshi Tomita , Yasurou Matsuzaki
发明人： Masao Taguchi , Hiroyoshi Tomita , Yasurou Matsuzaki
IPC分类号： H03K3013
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

2. 发明授权

US6154405A Semiconductor memory device having a dummy cell resetting the bit lines to a reset potential that is based on data read in a previous read data 失效
标题翻译：具有虚设单元的半导体存储器件，其将位线复位为基于在先前读取数据中读取的数据的复位电位
公开(公告)号：US6154405A
公开(公告)日：2000-11-28
申请号：US924315
申请日：1997-09-05
申请人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Hirohiko Mochizuki , Hiroyoshi Tomita , Yasurou Matsuzaki , Tadao Aikawa
发明人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Hirohiko Mochizuki , Hiroyoshi Tomita , Yasurou Matsuzaki , Tadao Aikawa
IPC分类号： G11C11/409 , G11C7/10 , G11C7/12 , G11C11/401 , G11C11/407 , G11C11/4096 , G11C7/02
CPC分类号： G11C11/4096 , G11C7/1048 , G11C7/12
摘要： A semiconductor memory device includes memory cells, word lines connected to the memory cells, bit lines connected to the memory cells, and a first circuit which resets the bit lines to a reset potential which is based on data read in a previous read cycle.
摘要翻译：半导体存储器件包括存储器单元，连接到存储器单元的字线，连接到存储器单元的位线，以及基于在先前读取周期中读取的数据将位线复位到复位电位的第一电路。

3. 发明授权

US6151274A System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor 有权
标题翻译：由同步半导体器件构成的系统，用于调整每个输入端和用于其的半导体器件的时序
公开(公告)号：US6151274A
公开(公告)日：2000-11-21
申请号：US440665
申请日：1999-11-16
申请人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima
发明人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima
IPC分类号： G06F13/42 , G06F1/10 , G06F1/12 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/4093 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/00 , H03L7/081 , H04L7/00 , G11C8/00
CPC分类号： H03L7/0805 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/133 , H03K5/135 , H03L7/00 , H03L7/0814 , G11C2207/108
摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.
摘要翻译：公开了一种用于实现这种系统的系统和半导体器件。该系统至少使用半导体器件来与外部时钟产生的内部时钟同步地检索输入信号，该输入信号与外部时钟同步地保持有效。即使在时钟与接收端的信号之间产生相位差的情况下，或者即使在时钟输入电路与接收端的半导体装置中的其他信号输入电路之间产生相位差的情况下，数据可以高速转移。在接收端的半导体器件的每个输入电路包括输入定时调整电路，用于调节施加到输入电路的时钟的相位，使得输入电路以有效和稳定的状态检索输入信号。在输入信号与输入信号和时钟之间的偏差相比较小的情况下，输入定时调整电路被多个输入电路共享。

4. 发明授权

US6028816A System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor 失效
公开(公告)号：US6028816A
公开(公告)日：2000-02-22
申请号：US924705
申请日：1997-09-05
申请人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima , Masao Nakano
发明人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima , Masao Nakano
IPC分类号： G06F13/42 , G06F1/10 , G06F1/12 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/4093 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/00 , H03L7/081 , H04L7/00 , G11C8/00
CPC分类号： H03L7/0805 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/133 , H03K5/135 , H03L7/00 , H03L7/0814 , G11C2207/108
摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.

5. 发明授权

US06205082B1 LSI device with memory and logics mounted thereon 有权
标题翻译：具有安装在其上的存储器和逻辑的LSI器件
公开(公告)号：US06205082B1
公开(公告)日：2001-03-20
申请号：US09304589
申请日：1999-05-04
申请人： Hiroyoshi Tomita , Yasurou Matsuzaki , Masao Taguchi
发明人： Hiroyoshi Tomita , Yasurou Matsuzaki , Masao Taguchi
IPC分类号： G11C800
CPC分类号： G11C7/1084 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C2207/105 , G11C2207/108 , H01L24/45 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/49175 , H01L2924/00014 , H01L2924/00
摘要： A data signal is output from an output circuit of a first chip and sent to a data input terminal in the second chip via a data lead line based on an output clock in first chip, which is sent to the second chip. And an input circuit in a second chip receives the data signal and transfers it inside in response to a transfer clock that has been generated from the output clock in the first chip. In synchronism with a single reference clock in the first chip, therefore, a data signal can be transferred to the second chip from the first chip at a high speed.
摘要翻译：数据信号从第一芯片的输出电路输出，并经由数据引线，基于第一芯片中的输出时钟发送到第二芯片中的数据输入端子，该输出时钟发送到第二芯片。并且第二芯片中的输入电路响应于从第一芯片中的输出时钟产生的传输时钟，接收数据信号并将其传送到内部。因此，与第一芯片中的单个参考时钟同步，数据信号可以从第一芯片高速传输到第二芯片。

6. 发明授权

US06510095B1 Semiconductor memory device for operating in synchronization with edge of clock signal 有权
标题翻译：用于与时钟信号的边沿同步操作的半导体存储器件
公开(公告)号：US06510095B1
公开(公告)日：2003-01-21
申请号：US10073231
申请日：2002-02-13
申请人： Yasurou Matsuzaki , Hiroyoshi Tomita , Masao Taguchi
发明人： Yasurou Matsuzaki , Hiroyoshi Tomita , Masao Taguchi
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C2207/2227
摘要： A command receiver circuit receives a command signal in synchronization with either a rising edge or a falling edge of a clock signal. A data input/output circuit starts an output of read data and an input of write data in synchronization with the edges of the clock signal which are set in response to reception timing of the command signal. Since the command signal can be received in synchronization with both edges of the clock signal, it is possible to halve a clock cycle when a reception rate is the same as that of the conventional art. As a result of this, in a system on which the semiconductor memory device is mounted, it is possible to halve the frequency of a system clock and to reduce power consumption of a clock synchronization circuit in the system, without reducing a data input/output rate for the semiconductor memory device.
摘要翻译：命令接收器电路与时钟信号的上升沿或下降沿同步地接收命令信号。数据输入/输出电路与响应命令信号的接收定时而设置的时钟信号的边沿同步地开始读取数据的输出和写入数据的输入。由于可以与时钟信号的两个边沿同步地接收命令信号，所以当接收速率与传统技术的接收速率相同时，可以将时钟周期减半。结果，在安装了半导体存储器件的系统中，可以将系统时钟的频率减半，并且可以降低系统中时钟同步电路的功耗，而不减少数据输入/输出速率为半导体存储器件。

7. 发明授权

US06509763B2 Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权
公开(公告)号：US06509763B2
公开(公告)日：2003-01-21
申请号：US10162565
申请日：2002-06-06
申请人： Masao Taguchi , Hiroyoshi Tomita , Yasurou Matsuzaki , Miki Yanagawa
发明人： Masao Taguchi , Hiroyoshi Tomita , Yasurou Matsuzaki , Miki Yanagawa
IPC分类号： G01R1900
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

8. 发明授权

US06272069B1 LSI device with memory and logics mounted thereon 有权
公开(公告)号：US06272069B1
公开(公告)日：2001-08-07
申请号：US09764446
申请日：2001-01-19
申请人： Hiroyoshi Tomita , Yasurou Matsuzaki , Masao Taguchi
发明人： Hiroyoshi Tomita , Yasurou Matsuzaki , Masao Taguchi
IPC分类号： G11C800
摘要： A data signal is output from an output circuit of a first chip and sent to a data input terminal in the second chip via a data lead line based on an output clock in first chip, which is sent to the second chip. And an input circuit in a second chip receives the data signal and transfers it inside in response to a transfer clock that has been generated from the output clock in the first chip. In synchronism with a single reference clock in the first chip, therefore, a data signal can be transferred to the second chip from the first chip at a high speed.

9. 发明授权

US6078514A Semiconductor device and semiconductor system for high-speed data transfer 失效
标题翻译：半导体器件和半导体系统，用于高速数据传输
公开(公告)号：US6078514A
公开(公告)日：2000-06-20
申请号：US61023
申请日：1998-04-16
申请人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
发明人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
IPC分类号： G11C11/41 , G11C7/10 , G11C7/22 , G11C11/401 , H01L21/60 , H01L25/00 , H01L27/10 , H01L25/04 , H01L23/36
CPC分类号： H01L23/60 , G11C7/1006 , G11C7/22 , H01L24/49 , H01L25/0655 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L24/48 , H01L27/0266 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/1305 , H01L2924/13091 , H01L2924/30105
摘要： A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.
摘要翻译：半导体系统包括至少一个逻辑芯片和布置成使得至少一个存储器芯片的一侧面向至少一个逻辑芯片的一侧的至少一个存储器芯片。所述半导体系统还包括为所述至少一个逻辑芯片提供的用于与相邻存储器芯片进行数据传输的第一输入/输出节点，为所述至少一个存储器芯片提供的第二输入/输出节点，用于与相邻的逻辑芯片以及容纳所述至少一个逻辑芯片和所述至少一个存储器芯片的封装，其中所述第一输入/输出节点沿着所述至少一个逻辑芯片的一侧布置，并且所述第二输入/输出节点是沿着至少一个存储器芯片的一侧布置。

10. 发明授权

US06907555B1 Self-test circuit and memory device incorporating it 有权
标题翻译：自检电路和结合其的存储器件
公开(公告)号：US06907555B1
公开(公告)日：2005-06-14
申请号：US09691115
申请日：2000-10-19
申请人： Yukihiro Nomura , Hiroyuki Fujimoto , Takahiro Suzuki , Tatsuya Kanda , Yasurou Matsuzaki , Masahiko Saitou , Hiroyoshi Tomita
发明人： Yukihiro Nomura , Hiroyuki Fujimoto , Takahiro Suzuki , Tatsuya Kanda , Yasurou Matsuzaki , Masahiko Saitou , Hiroyoshi Tomita
IPC分类号： G01R31/28 , G01R31/3185 , G06F12/16 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , G11C29/12 , G11C29/44
CPC分类号： G11C29/44
摘要： The present invention is a self-test circuit (BIST) incorporated in the memory device, which is activated in response to a test activation signal from outside. When this self-test circuit is activated in response to a test activation signal (WBIZ) from outside, it generates a test operation command (WBI-CMD), generates a test address (WBI-ADD), and generates test data (WBI-DATA). Furthermore, after the self-test circuit writes the test data to a memory cell, it effects a comparison to establish whether or not the read data that is read from this memory cell is the same as the test data that was written thereto and stores information as to the result of this comparison. This comparison result information is then output to the outside.
摘要翻译：本发明是一种结合在存储器件中的自检电路（BIST），其响应于来自外部的测试激活信号被激活。当该自检电路响应于来自外部的测试激活信号（WBIZ）被激活时，它产生测试操作命令（WBI-CMD），生成测试地址（WBI-ADD），并生成测试数据（WBI- 数据）。此外，在自检电路将测试数据写入存储单元之后，进行比较以确定从该存储单元读取的读取数据是否与写入的测试数据相同并存储信息关于这个比较的结果。然后将该比较结果信息输出到外部。

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