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1. 发明授权

US06807108B2 Semiconductor memory device having select circuit 失效
标题翻译：具有选择电路的半导体存储器件
公开(公告)号：US06807108B2
公开(公告)日：2004-10-19
申请号：US10266692
申请日：2002-10-09
申请人： Yukiko Maruyama , Takashi Itou
发明人： Yukiko Maruyama , Takashi Itou
IPC分类号： G11C1134
CPC分类号： G11C7/1084 , G11C7/1078 , G11C7/22 , G11C7/222
摘要： An input buffer circuit includes a first input buffer and a second input buffer. The first input buffer receives an external data signal and a reference potential to output an internal data signal. The second input buffer receives external data signals complementary to each other to output the internal data signal. The input buffer circuit causes either the first or second input buffer to operate in response to a control signal outputted from a control circuit. Due to this, this semiconductor memory device can correspond to various types of data processing systems.
摘要翻译：输入缓冲电路包括第一输入缓冲器和第二输入缓冲器。第一输入缓冲器接收外部数据信号和参考电位以输出内部数据信号。第二输入缓冲器接收彼此互补的外部数据信号以输出内部数据信号。输入缓冲电路使得第一或第二输入缓冲器响应于从控制电路输出的控制信号而工作。由此，该半导体存储器件可以对应于各种类型的数据处理系统。

2. 发明授权

US06424592B1 Semiconductor integrated circuit having circuit for correcting data output timing 失效
公开(公告)号：US06424592B1
公开(公告)日：2002-07-23
申请号：US09725855
申请日：2000-11-30
申请人： Yukiko Maruyama
发明人： Yukiko Maruyama
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/222 , G11C8/18
摘要： A semiconductor integrated circuit includes a DLL circuit generating an internal clock signal, a plurality of clock generators generating respective output clock signals based on the internal clock signal, a plurality of output buffers outputting to a plurality of data input/output pins data according to corresponding output clock signals respectively, and a selection circuit. The selection circuit outputs a code signal for allowing the timing of the earliest output clock signal to conform to the timing of the latest output clock signal. A predetermined clock generator adjusts the timing of the output clock signal according to the code signal.

3. 发明授权

US06319483B1 Gallium and/or indium separation and concentration method 失效
标题翻译：镓和/或铟分离浓缩法
公开(公告)号：US06319483B1
公开(公告)日：2001-11-20
申请号：US09481506
申请日：2000-01-12
申请人： Yoshito Kudo , Yukiko Maruyama
发明人： Yoshito Kudo , Yukiko Maruyama
IPC分类号： C22B5800
CPC分类号： C22B3/44 , C22B19/26 , C22B58/00 , C25C1/16 , Y02P10/234
摘要： It is possible to recover gallium and indium efficiently and at a low cost from solutions containing traces of gallium and indium. In particular, jarosite is produced by performing a specific treatment on a solution obtained by a two-stage neutralization treatment during the zinc leached residue treatment step of wet zinc refining, or on another solution containing traces of gallium and indium; the gallium and indium are separated and concentrated; an alkali is added to the jarosite; and the gallium is separated and concentrated by leaching. Calcium hydroxide or magnesium hydroxide is optionally added to the jarosite leached solution to perform purifying, sulfuric acid is added to the purified solution, neutralization is performed, basic gallium sulfate is precipitated, the precipitate is subjected to alkali leaching, and the gallium in the leached solution is electrolytically extracted, yielding metallic gallium.
摘要翻译：从含有痕量镓和铟的溶液中可以有效地以低成本回收镓和铟。特别地，通过对在锌精矿的锌浸出残渣处理工序中或通过含有痕量的镓和铟的另一种溶液进行两级中和处理得到的溶液进行特定处理而制造黄钾铁矾; 分离并浓缩镓和铟; 在黄钾铁矾中加入碱; 通过浸出分离并浓缩镓。将氢氧化钙或氢氧化镁任选加入到黄钾铁矾浸出溶液中进行纯化，向纯化溶液中加入硫酸，进行中和，碱式硫酸镓沉淀，析出物进行碱浸出，浸出后的镓电解提取溶液，产生金属镓。

4. 发明授权

US6166966A Semiconductor memory device including data output circuit capable of high speed data output 失效
标题翻译：半导体存储器件包括能够进行高速数据输出的数据输出电路
公开(公告)号：US6166966A
公开(公告)日：2000-12-26
申请号：US479258
申请日：2000-01-07
申请人： Yukiko Maruyama , Yutaka Ikeda , Kyoji Yamasaki
发明人： Yukiko Maruyama , Yutaka Ikeda , Kyoji Yamasaki
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1051
摘要： A semiconductor memory device includes an output control signal generation circuit for generating an output control signal to designate initiation of data output according to an external control signal, and a boosting circuit boosting an external power supply voltage. Each of the plurality of output control circuits generates an output permit signal with the output level of the boosting circuit as the activation level in response to activation of an output control signal. The output permit signals are transmitted to a plurality of output circuits by a corresponding one of a plurality of signal lines. Each of the plurality of output circuits drives the potential of a corresponding output terminal according to a read out data signal and an output permit signal.
摘要翻译：一种半导体存储器件包括：输出控制信号产生电路，用于根据外部控制信号产生一个输出控制信号以指定数据输出的启动;以及升压电路，提升外部电源电压。多个输出控制电路中的每一个响应于输出控制信号的激活而产生具有升压电路的输出电平作为激活电平的输出允许信号。输出许可信号通过多条信号线中相应的一条信号发送到多个输出电路。多个输出电路中的每一个根据读出的数据信号和输出许可信号驱动相应的输出端子的电位。

5. 发明授权

US06636455B2 Semiconductor memory device that operates in synchronization with a clock signal 失效
公开(公告)号：US06636455B2
公开(公告)日：2003-10-21
申请号：US10135507
申请日：2002-05-01
申请人： Yukiko Maruyama , Seiji Sawada
发明人： Yukiko Maruyama , Seiji Sawada
IPC分类号： G11C800
CPC分类号： G11C29/12015 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C11/401 , G11C11/4076 , G11C29/14 , G11C2207/229
摘要： This DDR SDRAM, in the normal operation mode, performs a writing operation having a writing latency and, in the testing mode, performs a writing operation without having a writing latency by receiving a data strobe signal and a data signal one clock cycle before a writing command. Therefore, the testing time is short even if the test is carried out at a low frequency.

6. 发明申请

US20150301935A1 MICROCOMPUTER AND NONVOLATILE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：微型计算机和非线性半导体器件
公开(公告)号：US20150301935A1
公开(公告)日：2015-10-22
申请号：US14382159
申请日：2012-03-02
申请人： Tamiyu KATO , Yukiko MARUYAMA , Shinya IZUMI , Kiyoshi NAKAKIMURA , Yoshihiro SEGUCHI
发明人： Tamiyu KATO , Yukiko MARUYAMA , Shinya IZUMI , Kiyoshi NAKAKIMURA , Yoshihiro SEGUCHI
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F9/30065 , G06F9/324 , G06F2212/7208
摘要： A program counter (12) updates an address by adding a first value or a second value. A code select circuit (14) selects, in accordance with the address of the program counter (12), one of an insert code retained in an insert code register set block (17) and corresponding to the address specified by the program counter (12), and an original code stored in a flash control code ROM (13) and having the address specified by the program counter (12). An instruction execution unit (15) executes the selected code. At least one of a plurality of original codes and the insert code is a multicycle instruction. The program counter (14) stops update of the address when the multicycle instruction is executed.
摘要翻译：程序计数器（12）通过添加第一值或第二值来更新地址。代码选择电路（14）根据程序计数器（12）的地址选择保存在插入代码寄存器设置块（17）中并与程序计数器（12）指定的地址相对应的插入代码）和存储在闪存控制代码ROM（13）中并具有由程序计数器（12）指定的地址的原始代码。指令执行单元（15）执行所选择的代码。多个原始代码和插入代码中的至少一个是多周期指令。当执行多周期指令时，程序计数器（14）停止更新地址。

7. 发明授权

US06687174B2 Semiconductor memory device capable of switching output data width 有权
标题翻译：能够切换输出数据宽度的半导体存储器件
公开(公告)号：US06687174B2
公开(公告)日：2004-02-03
申请号：US10336803
申请日：2003-01-06
申请人： Yukiko Maruyama , Yasuhiko Tsukikawa , Mikio Asakura , Takashi Itou
发明人： Yukiko Maruyama , Yasuhiko Tsukikawa , Mikio Asakura , Takashi Itou
IPC分类号： G11C700
CPC分类号： G11C11/4087 , G11C7/1045
摘要： In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between global I/O lines GIO to GIO and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.
摘要翻译：响应于输出数据宽度切换模式信号，预解码器区域+选择器区域将选择信号SEL0至SEL7和WORDA输出到WORDC到前置放大器+写入驱动器区域。前置放大器+写入驱动器区可以切换全局I / O线GIO <0>到GIO <7>之间的连接，并响应于这些选择信号切换数据总线。通过数据总线上的选择器电路等将读取数据输出到焊盘，由此可以在不进行由模式切换或地址变更引起的延迟时间的临界调整的情况下获得简单的结构。

8. 发明授权

US06535412B1 Semiconductor memory device capable of switching output data width 失效
公开(公告)号：US06535412B1
公开(公告)日：2003-03-18
申请号：US09557866
申请日：2000-04-24
申请人： Yukiko Maruyama , Yasuhiko Tsukikawa , Mikio Asakura , Takashi Itou
发明人： Yukiko Maruyama , Yasuhiko Tsukikawa , Mikio Asakura , Takashi Itou
IPC分类号： G11C700
CPC分类号： G11C11/4087 , G11C7/1045
摘要： In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between global I/O lines GIO to GIO and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.

9. 发明授权

US06426900B1 Synchronous semiconductor memory device performing data output in synchronization with external clock 失效
标题翻译：同步半导体存储器件与外部时钟同步执行数据输出
公开(公告)号：US06426900B1
公开(公告)日：2002-07-30
申请号：US09907589
申请日：2001-07-19
申请人： Yukiko Maruyama , Seiji Sawada
发明人： Yukiko Maruyama , Seiji Sawada
IPC分类号： G11C700
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1072 , G11C7/222 , H03K2005/00071 , H03L7/0814 , H03L7/089
摘要： A DLL circuit generates a control clock specifying an operating timing of a data output buffer according to an external clock. The DLL circuit includes a replica delay time adjusting section and a phase control section. The phase control section controls such that a feedback clock and the external clock becomes in phase. The replica delay time adjusting section adjusts a delay time of the feedback clock behind the control clock according to an operating condition serving as a factor for changing a processing time of the data output buffer.
摘要翻译： DLL电路根据外部时钟产生指定数据输出缓冲器的操作定时的控制时钟。 DLL电路包括复制延迟时间调整部分和相位控制部分。相位控制部分控制使得反馈时钟和外部时钟变为同相。复制延迟时间调整部根据用作改变数据输出缓冲器的处理时间的因素的操作条件来调整控制时钟后面的反馈时钟的延迟时间。

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