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1. 发明授权

US07161387B2 Semiconductor device and level conversion circuit 失效
公开(公告)号：US07161387B2
公开(公告)日：2007-01-09
申请号：US10947257
申请日：2004-09-23
申请人： Kyoji Yamasaki , Yasuhiko Tsukikawa
发明人： Kyoji Yamasaki , Yasuhiko Tsukikawa
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012 , H03K17/223
摘要： A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.

2. 发明授权

US07288965B2 Semiconductor device and level conversion circuit 失效
公开(公告)号：US07288965B2
公开(公告)日：2007-10-30
申请号：US11642726
申请日：2006-12-21
申请人： Kyoji Yamasaki , Yasuhiko Tsukikawa
发明人： Kyoji Yamasaki , Yasuhiko Tsukikawa
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012 , H03K17/223
摘要： A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.

3. 发明申请

US20050068062A1 Semiconductor device and level conversion circuit 失效
标题翻译：半导体器件和电平转换电路
公开(公告)号：US20050068062A1
公开(公告)日：2005-03-31
申请号：US10947257
申请日：2004-09-23
申请人： Kyoji Yamasaki , Yasuhiko Tsukikawa
发明人： Kyoji Yamasaki , Yasuhiko Tsukikawa
IPC分类号： H03K17/16 , H03K3/012 , H03K3/356 , H03K17/22 , H03K19/0185 , H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012 , H03K17/223
摘要： A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.
摘要翻译：电平转换电路，将从接收第一电源电压的第二内部电路输出的信号转换为具有与第一电源电压不同的电压电平的第二电源电压的电平的信号，以将其输出信号施加到第一内部电路设置有用于在第一电源电压被切断时切断通过电平转换电路中的通过电流的路径的机构。

4. 发明申请

US20070103197A1 Semiconductor device and level conversion circuit 失效
标题翻译：半导体器件和电平转换电路
公开(公告)号：US20070103197A1
公开(公告)日：2007-05-10
申请号：US11642726
申请日：2006-12-21
申请人： Kyoji Yamasaki , Yasuhiko Tsukikawa
发明人： Kyoji Yamasaki , Yasuhiko Tsukikawa
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012 , H03K17/223
摘要： A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.
摘要翻译：电平转换电路，将从接收第一电源电压的第二内部电路输出的信号转换为具有与第一电源电压不同的电压电平的第二电源电压的电平的信号，以将其输出信号施加到第一内部电路设置有用于在第一电源电压被切断时切断通过电平转换电路中的通过电流的路径的机构。

5. 发明授权

US06519194B2 Semiconductor memory device with a rapid packet data input, capable of operation check with low speed tester 失效
公开(公告)号：US06519194B2
公开(公告)日：2003-02-11
申请号：US09941609
申请日：2001-08-30
申请人： Mitsunori Tsujino , Kazutoshi Hirayama , Kyoji Yamasaki
发明人： Mitsunori Tsujino , Kazutoshi Hirayama , Kyoji Yamasaki
IPC分类号： G11C700
CPC分类号： G11C29/48
摘要： A semiconductor memory device uses in a test mode a clock signal from a tester to allow a test clock conversion circuit and a DLL circuit to generate a rapid internal clock. The internal clock is applied to serial-parallel conversion circuits subjecting received, packetized data to serial-parallel conversion, and an interface circuit receiving and decoding outputs from the serial-parallel conversion circuits and outputting a command such as ACT to a DRAM core. Furthermore, an internal packet generation circuit uses the internal clock to rapidly generate a testing packet signal. Thus the device's operation can be checked with a low speed tester, without externally receiving a rapid packet signal.

6. 发明授权

US06498760B2 Semiconductor device having test mode 有权
公开(公告)号：US06498760B2
公开(公告)日：2002-12-24
申请号：US09930174
申请日：2001-08-16
申请人： Kyoji Yamasaki
发明人： Kyoji Yamasaki
IPC分类号： G11C1100
CPC分类号： G11C5/145 , G11C29/12
摘要： An internal power supply potential generating circuit of a DRAM sets, at the time of a burn-in test, a first internal power supply potential for a wordline to an external power supply potential, maintains an internal power supply potential for a sense amplifier at an external reference potential, and maintains a second internal power supply potential for a peripheral circuit at a potential higher than the external reference potential only by a predetermined voltage. An early defect in a circuit portion to which the first internal power supply potential is applied and that in a circuit portion to which the second internal power supply potential is applied can be therefore accelerated separately from each other. Thus, a test efficiency is increased.

7. 发明授权

US5978299A Semiconductor memory device having a voltage lowering circuit of which supplying capability increases when column system is in operation 有权
公开(公告)号：US5978299A
公开(公告)日：1999-11-02
申请号：US222793
申请日：1998-12-30
申请人： Kyoji Yamasaki , Tadaaki Yamauchi , Mikio Asakura
发明人： Kyoji Yamasaki , Tadaaki Yamauchi , Mikio Asakura
IPC分类号： G11C11/413 , G11C5/14 , G11C11/401 , G11C11/407 , G11C11/409 , G11C11/34
CPC分类号： G11C5/147
摘要： A semiconductor memory device includes a memory cell array, peripheral circuits including a column decoder for connecting a word line, and a VDC circuit for peripherals, for generating an internal power supply voltage based on an external power supply voltage. VDC circuit for peripherals supplies the internal power supply voltage to peripheral circuits including the column decoder, other than the sense amplifier, output buffer and internal initial stage. The supplying capability of the VDC circuit for peripherals is increased in response to a VDCE signal which is output from a clock generation circuit when column decoder is activated. Therefore, even when power consumption in the peripheral circuit is increased as the column decoder is activated, sufficient power can be supplied to the peripheral circuit.

8. 发明授权

US5716889A Method of arranging alignment marks 失效
公开(公告)号：US5716889A
公开(公告)日：1998-02-10
申请号：US759199
申请日：1996-12-04
申请人： Takaharu Tsuji , Mikio Asakura , Kyoji Yamasaki
发明人： Takaharu Tsuji , Mikio Asakura , Kyoji Yamasaki
IPC分类号： G03F9/00 , H01L21/027 , H01L23/544 , H01L21/76
CPC分类号： G03F9/70 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S438/946 , Y10S438/975
摘要： A shot region includes a device region for forming a semiconductor device therein and a dicing region used for dicing. A portion of the peripheral edge portion of the shot region is defined by a portion of the peripheral edge portion of the device region. An alignment mark is arranged within the device region, and additional alignment marks are arranged within the dicing region. Thus, the number of the devices manufactured per wafer can be increased without degrading precision of alignment.

9. 发明授权

US06809576B1 Semiconductor integrated circuit device having two types of internal power supply circuits 失效
标题翻译：具有两种类型的内部电源电路的半导体集成电路器件
公开(公告)号：US06809576B1
公开(公告)日：2004-10-26
申请号：US09124962
申请日：1998-07-30
申请人： Kyoji Yamasaki
发明人： Kyoji Yamasaki
IPC分类号： G05F110
CPC分类号： G05F1/465
摘要： A resistance dividing circuit having the same voltage-dividing ratio as that of a voltage dividing circuit provided in a voltage-dividing voltage down-converting circuit divides a reference voltage employed in a direct feedback voltage down-converting circuit. The divided voltage is employed as the reference voltage for the voltage-dividing voltage down-converting circuit. A comparator cancels out temperature dependency of the resistance dividing circuit and the voltage dividing circuit by differential amplification, so that internal power supply voltages are identical in temperature dependency to each other. Thus, the internal power supply voltages generated by the direct feedback voltage down-converting circuit and the voltage-dividing voltage down-converting circuit have no difference in temperature dependency from each other.
摘要翻译：具有与分压电压降低转换电路中设置的分压电路相同的分压比的电阻分压电路将直接反馈电压降低转换电路中使用的参考电压除分。采用分压电压作为分压降压转换电路的基准电压。比较器通过差分放大来消除电阻分压电路和分压电路的温度依赖性，使得内部电源电压彼此相同。因此，由直接反馈电压降低转换电路和分压降压转换电路产生的内部电源电压在温度依赖性方面没有差异。

10. 发明授权

US6065143A Semiconductor memory device capable of fast testing without externally considering address scramble or data scramble 失效
标题翻译：半导体存储器件能够快速测试，无需外部考虑地址加扰或数据加扰
公开(公告)号：US6065143A
公开(公告)日：2000-05-16
申请号：US905542
申请日：1997-08-04
申请人： Kyoji Yamasaki , Yutaka Ikeda
发明人： Kyoji Yamasaki , Yutaka Ikeda
IPC分类号： G01R31/28 , G11C11/401 , G11C29/06 , G11C29/10 , G11C29/30 , G11C29/36 , G11C29/46 , G11C29/50 , H01L21/301 , H01L21/66 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , G11C29/00 , G11C7/00
CPC分类号： G11C29/50 , G11C29/30 , G11C29/36 , G11C11/401 , G11C29/46
摘要： A row address signal output from an internal row address generation circuit according to an output from a ring oscillator activated in response to an externally applied burn-in mode designation signal SBT, is scrambled by an operation circuit and then applied to a row decoder. Meanwhile, a signal output from a data output circuit in response to activation of signal SBT is scrambled by a data scrambler and checker pattern data is applied to a memory cell array such that it corresponds to a physical address of the memory cell array.
摘要翻译：根据来自外部施加的老化模式指定信号SBT激活的环形振荡器的输出，从内部行地址生成电路输出的行地址信号被运算电路加扰，然后施加到行解码器。同时，响应于信号SBT的激活而从数据输出电路输出的信号被数据加密器加扰，并且将检查器图案数据应用于存储单元阵列，使得其对应于存储单元阵列的物理地址。

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