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1. 发明授权

US3992635A N scale counter 失效
标题翻译： N比例计数器
公开(公告)号：US3992635A
公开(公告)日：1976-11-16
申请号：US632575
申请日：1975-11-17
申请人： Yasoji Suzuki , Kenshi Manabe , Teruaki Tanaka , Tomohisa Shigematsu
发明人： Yasoji Suzuki , Kenshi Manabe , Teruaki Tanaka , Tomohisa Shigematsu
IPC分类号： H03K23/52 , H03K21/02 , H03K23/54 , H03K23/30
CPC分类号： H03K21/02
摘要： An n scale counter includes a shift register having X number of unit delay circuits connected in series and each consisting of a plurality of insulated gate field effect transistors. The unit delay circuits of the shift register are simultaneously supplied with pulses to be counted and each of the delay cicuits is set or reset to an initial state. There is also provided a closed loop circuit including a first gate circuit connected to receive an output signal from the last stage delay circuit as one input terminal, and a logic circuit connected to receive output signals from the first gate circuit and, for example, the first stage delay circuit and produce to the input terminal of the first stage delay circuit an output signal indicating coincidence or incoincidence of its input signals. The counter is capable of counting pulses of (2.sup.x -1) at maximum. A second gate circuit is provided to apply its output signal to the other input terminal of the first gate circuit and output signals of a predetermined combination from the unit delay circuits are supplied to the second gate circuit so that the counter can function as a counter with a counting capacity smaller than that of (2.sup.x -1).
摘要翻译： n比例计数器包括具有X个单元延迟电路的移位寄存器，它们串联连接，并且每个由多个绝缘栅场效应晶体管组成。移位寄存器的单位延迟电路同时提供要计数的脉冲，并且每个延迟电路被设置或复位到初始状态。还提供了一种闭环电路，包括连接成将来自最后级延迟电路的输出信号作为一个输入端子接收的第一门电路和连接成接收来自第一门电路的输出信号的逻辑电路，例如，第一级延迟电路，并向第一级延迟电路的输入端产生指示其输入信号一致或不一致的输出信号。计数器最多能够计数（2x-1）的脉冲。提供第二门电路以将其输出信号施加到第一门电路的另一输入端，并且将来自单元延迟电路的预定组合的输出信号提供给第二门电路，使得计数器可用作具有计数容量小于（2x-1）的计数容量。

2. 发明授权

US4088958A Integrated circuit for a programmable television receiver 失效
标题翻译：可编程电视接收机的集成电路
公开(公告)号：US4088958A
公开(公告)日：1978-05-09
申请号：US722761
申请日：1976-09-13
申请人： Yasoji Suzuki , Tomohisa Shigematsu , Nawoyuki Kokado , Yukinori Kudo
发明人： Yasoji Suzuki , Tomohisa Shigematsu , Nawoyuki Kokado , Yukinori Kudo
IPC分类号： G04G15/00 , G05B19/02 , G05B19/045 , G09G5/00 , G09G5/22 , H03J5/02 , H04B1/06 , H04N5/44 , H04B1/16
CPC分类号： H03J5/0245 , G04G15/006 , G05B19/045 , H04N5/45
摘要： An integrated circuit for a programmable television receiver comprises a memory for storing a plurality of programs, a digital clock and a character generating circuit for generating character signals for displaying the programs in the memory and/or time of the digital clock on the screen of a television receiver. The integrated circuit uses dynamic circuits to reduce the number of elements required, and CMOS transistors to attain a lower power dissipation.
摘要翻译：一种用于可编程电视接收机的集成电路包括用于存储多个节目的存储器，数字时钟和字符产生电路，用于产生用于在存储器中显示节目的字符信号和/或数字时钟的时间在电视接收机。该集成电路使用动态电路来减少所需的元件数量，并使用CMOS晶体管来实现更低的功耗。

3. 发明授权

US4930105A Nonvolatile semiconductor memory device with a double gate structure 失效
标题翻译：具有双栅极结构的非易失性半导体存储器件
公开(公告)号：US4930105A
公开(公告)日：1990-05-29
申请号：US178609
申请日：1988-04-07
申请人： Osamu Matsumoto , Tadashi Maruyama , Hiroyoshi Murata , Isao Abe , Tomohisa Shigematsu , Kazuyoshi Shinada , Yasoji Suzuki , Ichiro Kobayashi
发明人： Osamu Matsumoto , Tadashi Maruyama , Hiroyoshi Murata , Isao Abe , Tomohisa Shigematsu , Kazuyoshi Shinada , Yasoji Suzuki , Ichiro Kobayashi
IPC分类号： G11C17/00 , G11C16/04 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0416 , G11C16/0425
摘要： A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.

4. 发明授权

US4912749A Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US4912749A
公开(公告)日：1990-03-27
申请号：US149606
申请日：1988-01-28
申请人： Tadashi Maruyama , Yukio Wada , Tomohisa Shigematsu , Yasoji Suzuki , Makoto Yoshizawa
发明人： Tadashi Maruyama , Yukio Wada , Tomohisa Shigematsu , Yasoji Suzuki , Makoto Yoshizawa
IPC分类号： G11C17/00 , B42D15/02 , B42D15/10 , G03H1/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/26 , G11C11/34
CPC分类号： G11C16/26 , G11C16/0433 , G11C16/10
摘要： In a nonvolatile semiconductor memory according to the invention, a power source voltage of 5 V used in an ordinary read mode is applied to a read line in the data read mode without changing its value. If a write line, a selection gate line, a control gate line, and a read line are respectively set at 0 V, 5 V, 0 V, and 5 V in the data read mode, the potential at an n-type diffusion layer becomes 0 V. In this case, the potential at the control gate line is 0 V, and the potential at a floating gate electrode becomes substantially 0 V. That is, an electric field is not applied to a thin insulating film located between the floating gate electrode and the n-type diffusion layer. As a result, electron injection and discharge due to the tunnel effect do not occur.

5. 发明授权

US4870615A Nonvolatile floating gate semiconductor memory device 失效
标题翻译：非易失性浮栅半导体存储器件
公开(公告)号：US4870615A
公开(公告)日：1989-09-26
申请号：US150290
申请日：1988-01-29
申请人： Tadashi Maruyama , Yukio Wada , Tomohisa Shigematsu , Yasoji Suzuki , Makoto Yoshizawa
发明人： Tadashi Maruyama , Yukio Wada , Tomohisa Shigematsu , Yasoji Suzuki , Makoto Yoshizawa
IPC分类号： G11C17/00 , G11C16/04 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0433
摘要： A nonvolatile semiconductor memory device comprises a cell transistor formed of a floating gate type MOS transistor, for storing an electric charge, whose gate is connected to a control gate line layer, a first selecting transistor formed of an MOS transistor, whose gate is connected to a read gate line layer, whose source-drain path is connected at one end to a read line layer, and at the other end to one terminal of the source-drain path of the cell transistor, and a second selecting transistor formed of an MOS transistor, whose gate is connected to a write gate line layer, whose source-drain path is connected at one end to a write line layer, and at the other end to the other terminal of the source-drain path of a cell transistor. A power source voltage of 5 V can be supplied to the read line layer in the read mode.

6. 发明授权

US4143391A Integrated circuit device 失效
标题翻译：集成电路设备
公开(公告)号：US4143391A
公开(公告)日：1979-03-06
申请号：US917176
申请日：1978-06-20
申请人： Yasoji Suzuki , Tomohisa Shigematsu
发明人： Yasoji Suzuki , Tomohisa Shigematsu
IPC分类号： H01L27/092 , H01L27/02
CPC分类号： H01L27/0921
摘要： An integrated circuit device includes complementary MOS circuit elements formed in an N type semiconductor substrate with a P type region formed in the substrate. Protective circuit elements connected to an input terminal are formed in an area of the substrate other than the region thereof having the complementary MOS circuit elements formed therein. At least one of the regions constituting the protective circuit elements is formed in a P type additional region formed in the area of the N type substrate.

7. 发明授权

US06046626A Voltage transfer circuit and a booster circuit, and an IC card comprising the same 失效
标题翻译：电压传输电路和升压电路，以及包括该电路的IC卡
公开(公告)号：US06046626A
公开(公告)日：2000-04-04
申请号：US3946
申请日：1998-01-08
申请人： Yukihiro Saeki , Yasoji Suzuki
发明人： Yukihiro Saeki , Yasoji Suzuki
IPC分类号： G11C11/413 , G06K19/07 , G11C11/407 , G11C16/06 , H02M3/07 , H03K19/0948 , G05F3/02
CPC分类号： H02M3/073
摘要： A voltage transfer circuit comprises a first MOS transistor of a first channel type having a drain terminal connected to a first node supplied with a predetermined voltage, a source terminal connected to a second node, and a gate terminal, a second MOS transistor of a first channel type having a source terminal connected to the second node, a drain terminal connected to the gate terminal of the first MOS transistor, and a gate terminal supplied with a clock signal, as well as a third MOS transistor of a second channel type having a drain terminal connected to the drain terminal of the second MOS transistor, a source terminal connected to a third node supplied with a reference voltage, and a gate terminal supplied with the clock signal.
摘要翻译：电压传输电路包括第一通道类型的第一MOS晶体管，其具有连接到被提供有预定电压的第一节点的漏极端子，连接到第二节点的源极端子和栅极端子，第一MOS晶体管的第一沟道型，具有连接到第二节点的源极端子，连接到第一MOS晶体管的栅极端子的漏极端子和提供有时钟信号的栅极端子，以及具有第二沟道类型的第三MOS晶体管，其具有漏极端子连接到第二MOS晶体管的漏极端子，连接到提供有参考电压的第三节点的源极端子和被提供有时钟信号的栅极端子。

8. 发明授权

US6020869A Multi-gray level display apparatus and method of displaying an image at many gray levels 失效
公开(公告)号：US6020869A
公开(公告)日：2000-02-01
申请号：US841389
申请日：1997-04-30
申请人： Itsuo Sasaki , Yasoji Suzuki , Hirofumi Kato , Isao Arita , Toshio Yanagisawa , Kazuyoshi Yamamoto , Hiroyoshi Murata , Hiroyuki Hamagawa
发明人： Itsuo Sasaki , Yasoji Suzuki , Hirofumi Kato , Isao Arita , Toshio Yanagisawa , Kazuyoshi Yamamoto , Hiroyoshi Murata , Hiroyuki Hamagawa
IPC分类号： G09G3/20 , G09G3/36 , G09G3/28 , G09G3/30 , G09G5/10
CPC分类号： G09G3/3648 , G09G2310/027 , G09G3/2007 , G09G3/2018
摘要： A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit 311 for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit 321 for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit 341 for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit 311 or the second gray-level pattern generating circuit 321 when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.

9. 发明授权

US4558234A Complementary MOSFET logic circuit 失效
标题翻译：互补MOSFET逻辑电路
公开(公告)号：US4558234A
公开(公告)日：1985-12-10
申请号：US652429
申请日：1984-09-20
申请人： Yasoji Suzuki , Kenji Matsuo
发明人： Yasoji Suzuki , Kenji Matsuo
IPC分类号： H03K19/017 , H03K19/0175 , H03K19/0944 , H03K19/092 , H03K19/003 , H03K19/01 , H03K19/094
CPC分类号： H03K19/09448 , H03K19/01721 , H03K19/017518
摘要： Disclosed is a complementary MOSFET logic circuit having a complementary MOS inverter with a pregiven ratio of the channel widths of a P channel MOSFET and an N channel MOSFET and pregiven threshold voltages of the FETs so as to have an input voltage characteristic adapted to an output voltage characteristic, and a buffer circuit which includes a bipolar transistor for receiving at the base thereof a signal from the output terminal of the complementary MOS inverter and an N channel MOSFET for receiving at the gate thereof an input signal applied to the complementary MOS inverter. The inverter and buffer are connected in series to one another between a high potential applying point and a low potential applying point, and a signal corresponding to a logic output signal of the complementary MOS inverter is produced at the output terminal thereof.
摘要翻译：公开了具有互补MOS反相器的互补MOSFET逻辑电路，其具有P沟道MOSFET和N沟道MOSFET的沟道宽度的预制比和FET的预定阈值电压，以便具有适于输出电压的输入电压特性特性和缓冲电路，其包括用于在其基极处接收来自互补MOS反相器的输出端的信号的双极晶体管和用于在其栅极处接收施加到互补MOS反相器的输入信号的N沟道MOSFET。反相器和缓冲器在高电位施加点和低电位施加点之间彼此串联连接，并且在其输出端产生与互补MOS反相器的逻辑输出信号相对应的信号。

10. 发明授权

US4546327A Analog signal power amplifier circuit 失效
标题翻译：模拟信号功率放大器电路
公开(公告)号：US4546327A
公开(公告)日：1985-10-08
申请号：US513308
申请日：1983-07-13
申请人： Yasoji Suzuki , Itsuo Sasaki , Shouji Abou
发明人： Yasoji Suzuki , Itsuo Sasaki , Shouji Abou
IPC分类号： H03F3/20 , H03F3/213 , H03F3/45 , H03F3/72
CPC分类号： H03F3/213 , H03F3/45183 , H03F3/72 , H03F2200/03 , H03F2200/507 , H03F2200/522 , H03F2203/45508 , H03F2203/45674
摘要： A signal corresponding to an analog input signal is supplied to one of two input terminals of a two-input, one-output MOS differential amplifier. A reference voltage signal is supplied to the other of the two input terminals of the MOS differential amplifier. A bipolar transistor having one end connected to an analog signal output terminal is driven by a signal from the output terminal of the MOS differential amplifier. A loudspeaker is driven by the bipolar transistor.
摘要翻译：对应于模拟输入信号的信号被提供给双输入一输出MOS差分放大器的两个输入端中的一个。将参考电压信号提供给MOS差分放大器的两个输入端子中的另一个。具有连接到模拟信号输出端的一端的双极晶体管由来自MOS差分放大器的输出端的信号驱动。扬声器由双极晶体管驱动。

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