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1. 发明授权

US4114052A Presettable dynamic delay flip-flop circuit 失效
标题翻译：预置动态延迟翻转电路
公开(公告)号：US4114052A
公开(公告)日：1978-09-12
申请号：US801254
申请日：1977-05-27
申请人： Kenshi Manabe , Kouichirou Satou
发明人： Kenshi Manabe , Kouichirou Satou
IPC分类号： H03K3/037 , H03K3/286 , H03K23/00 , H03K23/58 , H03K23/64 , H03K23/66 , H03K3/353 , H03K21/30 , H03K23/30
CPC分类号： H03K23/665 , H03K3/037
摘要： A presettable dynamic delay flip-flop circuit including two first and second series-connected 1/2 bit delay circuits, a gate circuit for supplying these delay circuits with a control signal for controlling their operation, and a switching circuit for supplying the second delay circuit with preset data capable of freely presetting the voltage level of an output signal from said flip-flop circuit. The delay circuits and switching circuit are respectively formed of clocked inverters. The flip-flop circuit is formed of a small number of elements and operated at high frequency.

2. 发明授权

US3803429A Switchable frequency tone filter and detector with high speed switching capability 失效
标题翻译：可切换频率滤波器和具有高速开关能力的检测器
公开(公告)号：US3803429A
公开(公告)日：1974-04-09
申请号：US30444072
申请日：1972-11-07
申请人： MOTOROLA INC
发明人： WIECZOREK A , POORVIN R
IPC分类号： H04B1/10 , H03H11/12 , H04L27/26 , H04Q1/30 , H04W88/02 , H03K23/30
CPC分类号： H04W88/027 , H03H11/1252 , H04L27/26
摘要： An electronically variable tone signal filter and detector for receiving a plurality of tone signals in sequence. The filter circuit has a predetermined energy build up and decay rate and includes a first circuit element for determining the tone signal frequency coupled through the filter, and a second circuit element for determining the bandwidth of the filter. A first circuit is coupled to the first circuit element and is responsive to control signals coupled thereto to change the tone signal frequency the filter circuit couples therethrough. A second circuit is coupled to the second element and responsive to control signals coupled thereto to increase the bandwidth of the filter circuit. The increased bandwidth causes an increase in the energy decay rate of the filter.

3. 发明授权

US3500068A Pulse generating and registering circuit having means for controlling the timing of registering a count and generating a count 失效
标题翻译：脉冲发生和注册电路，用于控制注册计数和生成计数的时间
公开(公告)号：US3500068A
公开(公告)日：1970-03-10
申请号：US3500068D
申请日：1967-01-03
申请人： BURROUGHS CORP
发明人： HOLZ GEORGE E
IPC分类号： H03K3/352 , H03K3/78 , H03K23/00 , H03K23/30 , H03K21/36
CPC分类号： H03K3/352 , H03K3/78 , H03K23/002

4. 发明授权

US3430067A Frequency divider system 失效
标题翻译：频率分频器系统
公开(公告)号：US3430067A
公开(公告)日：1969-02-25
申请号：US3430067D
申请日：1966-01-14
申请人： SENCORE INC
发明人： BAUM ROBERT E
IPC分类号： H03B19/00 , H04N17/00 , H03K21/00 , H03K23/22 , H03K23/30
CPC分类号： H04N17/00 , H03B19/00

5. 发明授权

US4293919A Level sensitive scan design (LSSD) system 失效
标题翻译：液位敏感扫描设计（LSSD）系统
公开(公告)号：US4293919A
公开(公告)日：1981-10-06
申请号：US66130
申请日：1979-08-13
申请人： Sumit Dasgupta , Prabhakar Goel , Thomas W. Williams
发明人： Sumit Dasgupta , Prabhakar Goel , Thomas W. Williams
IPC分类号： G06F7/00 , G01R31/3185 , G06F11/22 , G06F7/48 , G06F11/00 , H03K23/30
CPC分类号： G01R31/318541 , G01R31/318583
摘要： One of the significant features of the invention, as in U.S. Pat. No. 3,783,254, is the implementation of shift register latches as basic building blocks in a logic organization and system with combinational logic networks which provide the excitation for the shift register latches. These shift register latches in the invention as well as in the patent contain a pair of latches where one is a "master" latch and another a "slave". The structure in the patent requires the "master" and "slave" latches to be part of the shift register for scan-in/scan-out. However, only the "master" may be set with data from the logic system surrounding it while the "slave" may only be set with data which previously resided in the related "master" latch. Thus, in those logic organizations where only the "master" latch output is required, the usefulness of the "slave" latch is limited to scan-in/scan-out. In the shift register latch of the invention, the "slave" latch must be set with the data that resided in the related "master" latch during scan-in/scan-out. However, in logic systems requiring the use of only one latch of the shift register latch, both "master" and "slave" latches can perform independent of the other; that is, each latch may be set with data from the logic system without any influence from the other latch in the same shift register latch. Similarly, both "master" and "slave" may feed different sections of the logic surrounding it.
摘要翻译：本发明的重要特征之一，如美国专利第3,783,254号是在具有为移位寄存器锁存器提供激励的组合逻辑网络的逻辑组织和系统中作为基本构建块的移位寄存器锁存器的实现。本发明以及专利中的这些移位寄存器锁存器包含一对锁存器，其中一个是“主”锁存器，另一个是“从设备”。该专利中的结构要求“主”和“从”锁存器成为扫描/扫描输出的移位寄存器的一部分。然而，只有“主”可以用来自其周围的逻辑系统的数据设置，而“从”只能用先前位于相关的“主”锁存器中的数据设置。因此，在仅需要“主”锁存器输出的那些逻辑组织中，“从”锁存器的有用性仅限于扫描/扫描输出。在本发明的移位寄存器锁存器中，“从”锁存器必须与在扫描/扫描期间存储在相关“主”锁存器中的数据一起设置。然而，在仅需要使用移位寄存器锁存器的一个锁存器的逻辑系统中，“主”和“从”锁存器可独立于另一个执行; 也就是说，每个锁存器可以被设置有来自逻辑系统的数据，而不受来自同一移位寄存器锁存器中的另一个锁存器的任何影响。类似地，“主”和“从”两者可以馈送围绕它的逻辑的不同部分。

6. 发明授权

US4075464A Incrementer/decrementer circuit 失效
标题翻译：增压器/减速电路
公开(公告)号：US4075464A
公开(公告)日：1978-02-21
申请号：US792617
申请日：1977-05-02
申请人： Thomas J. Davies, Jr.
发明人： Thomas J. Davies, Jr.
IPC分类号： H03K21/02 , H03K23/42 , G06M3/14 , H03K23/30
CPC分类号： H03K23/42 , H03K21/026
摘要： A digital circuit for sensing the signal on a data bus, selectively incrementing or decrementing the binary signal and reapplying it to the bus. The circuitry includes a binary counter comprising a temporary storage cell for each bus conductor. The output of each cell controls the conduction through an adjacent portion of a pre-charged conductor which is periodically discharged at the least significant digit cell and which, when charged adjacent a higher order cell, will inhibit the toggling of that cell. All bus lines are pre-charged to a binary "1" at a particular instant followed by the discharge to "0" of those lines whose respective cells contain a binary "0".

7. 发明授权

US3989957A Count-of-ten semiconductor structure 失效
标题翻译：十数十个半导体结构
公开(公告)号：US3989957A
公开(公告)日：1976-11-02
申请号：US627554
申请日：1975-10-31
申请人： Patrick A. Tuccu
发明人： Patrick A. Tuccu
IPC分类号： H01L27/02 , H03K3/288 , H03K21/06 , H03K23/30
CPC分类号： H03K21/38 , H01L27/0233 , H03K3/288
摘要： A count of ten divider uses plural divide-by-two circuits, plural NOR gates and an inverter formed in a semiconductor body all of the foregoing being in a collector-up configuration.
摘要翻译：十位分频器的计数器使用多个分频电路，多个NOR门和形成在半导体本体中的逆变器都是集电极配置。

8. 发明授权

US3983411A Frequency divider 失效
公开(公告)号：US3983411A
公开(公告)日：1976-09-28
申请号：US580569
申请日：1975-05-27
申请人： Jakob Luscher , Andreas Rusznyak
发明人： Jakob Luscher , Andreas Rusznyak
IPC分类号： H03K25/00 , G04G3/02 , H03K23/44 , H03K23/30
CPC分类号： G04G3/02 , H03K23/44
摘要： A binary frequency-divider stage for an electronic wristwatch comprises a set of insulated-gate field-effect transistors (IGFETs) of one and the same conductivity type, one (T.sub.1) of these IGFETs and an associated series capacitor (C.sub.1) forming an amplifier located between one bus bar (M) of a d-c supply and a first one (11) of two a-c control leads carrying a pair of bipolar pulse trains (.PHI..sub.1, .PHI..sub.2) of opposite phase. An incoming pulse sequence (V.sub.E1), of a cadence to be halved, is in phase with the pulse train (.PHI..sub.2) on the other control lead (12) and may be derived directly therefrom (FIG. 5). The gate capacitance of the first IGFET (T.sub.1) can be charged in two steps by a first charging circuit including two IGFETs (T.sub.2, T.sub.3) which are alternately turned on by respective control pulses (.PHI..sub.1, .PHI..sub.2) applied to their gates. A normally blocked discharging circuit, including two other IGFETs (T.sub.4, T.sub.5), serves to discharge that gate capacitance, the gate capacitance of one of the IGFETs (T.sub.5) of this discharging circuit being chargeable through a second charging circuit including two further IGFETs (T.sub.6, T.sub.7). The fifth IGFET (T.sub.5) is rendered conductive upon the successive occurrence of an incoming pulse (V.sub.E1) and a first control pulse (.PHI..sub.1) respectively turning on the sixth and seventh IGFETs (T.sub.6, T.sub.7). Upon the conduction of the fourth IGFET (T.sub.4), in response to the next incoming pulse, the first IGFET (T.sub.1) is cut off whereby the next-following first control pulse (.PHI..sub.1) gives rise to an outgoing pulse (V.sub.E2) on the junction (d) between that transistor and its series capacitor (C.sub.1). The gate of the fifth IGFET (T.sub.5) is discharged through an eighth IGFET (T.sub.8) controlled by the outgoing pulse. The third IGFET (T.sub.3) may be included in the normally blocked discharging circuit for the gate of the first IGFET (T.sub.1); alternatively, to prevent a premature discharge of that gate, the common terminal of the fourth and fifth IGFETs (T.sub.4, T.sub.5) may be recharged, after each incoming pulse (VE.sub.1) discharging this common terminal, by a ninth IGFET (T.sub.9) responsive to the first control pulse (.PHI..sub.1).

9. 发明授权

US4506167A High speed logic flip-flop latching arrangements including input and feedback pairs of transmission gates 失效
标题翻译：包括传输门的输入和反馈对的高速逻辑触发器锁存装置
公开(公告)号：US4506167A
公开(公告)日：1985-03-19
申请号：US469541
申请日：1982-05-26
申请人： Wendell L. Little , Barry W. Herold
发明人： Wendell L. Little , Barry W. Herold
IPC分类号： H03K3/037 , H03K3/356 , H03K3/3562 , H03K19/017 , H03K23/30
CPC分类号： H03K3/35625 , H03K3/037 , H03K3/356156
摘要： A high speed logic latching circuit consists of a pair of inverters and feedback switches used to latch the inverters. A pair of input switching means allows data to enter the latch when the latch is disabled. This configuration allows for high speed, reduced substrate area and true complementary outputs.
摘要翻译：高速逻辑锁存电路由用于锁存逆变器的一对逆变器和反馈开关组成。当禁止锁存时，一对输入切换装置允许数据进入锁存器。该配置允许高速度，减少的基板面积和真正的互补输出。

10. 发明授权

US4357546A Integrated frequency divider circuit 失效
标题翻译：集成分频电路
公开(公告)号：US4357546A
公开(公告)日：1982-11-02
申请号：US208096
申请日：1980-11-18
申请人： George A. Govaert
发明人： George A. Govaert
IPC分类号： H03K3/289 , H03K3/288 , H03K23/00 , H03K23/52 , H03K29/00 , H03K23/30
CPC分类号： H03K3/288
摘要： A frequency divider circuit realized by means of two piled bistable transistor pairs, the signal, whose frequency is to be divided, being applied in phase to the emitters of the lower transistor pair and in phase opposition to the auxiliary emitters of the upper transistor pair.
摘要翻译：通过两个堆叠的双稳态晶体管对实现的分频器电路，其频率被分频的信号被相位地施加到下晶体管对的发射极，并与上部晶体管对的辅助发射极相对置。

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