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1. 发明授权

US08163640B2 Metal gate compatible electrical fuse 失效
标题翻译：金属门兼容电保险丝
公开(公告)号：US08163640B2
公开(公告)日：2012-04-24
申请号：US11874385
申请日：2007-10-18
申请人： Xiangdong Chen , Deok-kee Kim , Chandrasekharan Kothandaraman
发明人： Xiangdong Chen , Deok-kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L27/06 , H01L21/3205
CPC分类号： H01L27/0617 , H01L23/5256 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.
摘要翻译：在用于金属栅电极的金属栅极层上形成电介质材料层，然后通过光刻图案形成电介质材料部分，随后在其上形成多晶半导体层。在包含金属栅极层和多晶半导体层的垂直邻接堆叠的半导体基板的区域中形成采用金属栅电极的半导体器件。形成有电熔丝形状的材料堆叠形成在半导体衬底的另一区域中，该区域包含金属栅极层，电介质材料部分和多晶半导体层的垂直叠层。在多晶半导体层的金属化之后，在将电熔丝与金属栅极层分离开的电介质材料部分上形成包含多晶半导体部分和金属半导体合金部分的电熔丝。

2. 发明申请

US20090101989A1 METAL GATE COMPATIBLE ELECTRICAL FUSE 失效
标题翻译：金属门兼容电保险丝
公开(公告)号：US20090101989A1
公开(公告)日：2009-04-23
申请号：US11874385
申请日：2007-10-18
申请人： Xiangdong Chen , Deok-kee Kim , Chandrasekharan Kothandaraman
发明人： Xiangdong Chen , Deok-kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L27/06 , H01L21/3205
CPC分类号： H01L27/0617 , H01L23/5256 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.
摘要翻译：在用于金属栅电极的金属栅极层上形成电介质材料层，然后通过光刻图案形成电介质材料部分，随后在其上形成多晶半导体层。在包含金属栅极层和多晶半导体层的垂直邻接堆叠的半导体基板的区域中形成采用金属栅电极的半导体器件。形成有电熔丝形状的材料堆叠形成在半导体衬底的另一区域中，该区域包含金属栅极层，电介质材料部分和多晶半导体层的垂直叠层。在多晶半导体层的金属化之后，在将电熔丝与金属栅极层分离开的电介质材料部分上形成包含多晶半导体部分和金属半导体合金部分的电熔丝。

3. 发明申请

US20100181643A1 EFUSE WITH PARTIAL SIGE LAYER AND DESIGN STRUCTURE THEREFOR 有权
标题翻译：具有部分信号层及其设计结构
公开(公告)号：US20100181643A1
公开(公告)日：2010-07-22
申请号：US12354996
申请日：2009-01-16
申请人： Chandrasekharan Kothandaraman , Deok-kee Kim , Dureseti Chidambarrao , William K. Henson
发明人： Chandrasekharan Kothandaraman , Deok-kee Kim , Dureseti Chidambarrao , William K. Henson
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse includes a fuse link region, a first region and a second region. The fuse link region electrically connects the first region to the second region. A SiGe layer is disposed only in the fuse link region and the first region.
摘要翻译：熔丝包括熔丝链接区域，第一区域和第二区域。熔丝链路区域将第一区域电连接到第二区域。 SiGe层仅设置在熔丝连接区域和第一区域中。

4. 发明授权

US07732893B2 Electrical fuse structure for higher post-programming resistance 失效
标题翻译：电熔丝结构，具有更高的后编程电阻
公开(公告)号：US07732893B2
公开(公告)日：2010-06-08
申请号：US11683071
申请日：2007-03-07
申请人： Subramanian S. Iyer , Deok-Kee Kim , Chandrasekharan Kothandaraman , Byeongju Park
发明人： Subramanian S. Iyer , Deok-Kee Kim , Chandrasekharan Kothandaraman , Byeongju Park
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an electrical fuse structure for achieving a post-programming resistance distribution with higher resistance values and to enhance the reliability of electrical fuse programming. A partly doped electrical fuse structure with undoped semiconductor material in the cathode combined with P-doped semiconductor material in the fuselink and anode is disclosed and the data supporting the superior performance of the disclosed electrical fuse is shown.
摘要翻译：本发明提供一种用于实现具有更高电阻值的后编程电阻分布并提高电熔丝编程的可靠性的电熔丝结构。公开了在阴极中与掺杂了P掺杂的半导体材料结合在阴极中的未掺杂半导体材料的部分掺杂的电熔丝结构，并且示出了所公开的电熔丝的优异性能的数据。

5. 发明授权

US07713792B2 Fuse structure including monocrystalline semiconductor material layer and gap 有权
标题翻译：保险丝结构包括单晶半导体材料层和间隙
公开(公告)号：US07713792B2
公开(公告)日：2010-05-11
申请号：US11870007
申请日：2007-10-10
申请人： Anil Kumar Chinthakindi , Deok-Kee Kim , Chandrasekharan Kothandaraman , Byeongju Park
发明人： Anil Kumar Chinthakindi , Deok-Kee Kim , Chandrasekharan Kothandaraman , Byeongju Park
IPC分类号： H01L21/02 , H01L29/00
CPC分类号： H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure, a method for fabricating the fuse structure and a method for programming a fuse within the fuse structure each use a fuse material layer that is used as a fuse, and located upon a monocrystalline semiconductor material layer in turn located over a substrate. At least part of the monocrystalline semiconductor material layer is separated from the substrate by a gap. Use of the monocrystalline semiconductor material layer, as well as the gap, provides for enhanced uniformity and reproducibility when programming the fuse.
摘要翻译：熔丝结构，制造熔丝结构的方法和用于对熔丝结构内的熔丝进行编程的方法各自使用用作熔丝的熔丝材料层，并且依次位于单晶半导体材料层上而位于衬底上。至少部分单晶半导体材料层通过间隙与衬底分离。单晶半导体材料层的使用以及间隙，在编程保险丝时提供了增强的均匀性和再现性。

6. 发明授权

US07550323B2 Electrical fuse with a thinned fuselink middle portion 失效
标题翻译：电熔丝带有细长的中间部分
公开(公告)号：US07550323B2
公开(公告)日：2009-06-23
申请号：US11835800
申请日：2007-08-08
申请人： Dureseti Chidambarrao , William K. Henson , Deok-kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semiconductor portion has a thin metal layer, which upon annealing produces a thinner metal semiconductor alloy portion than surrounding metal semiconductor alloy portion on the fuselink semiconductor portion. Alternatively, a middle portion of the metal semiconductor alloy having a uniform thickness throughout the fuselink may be lithographically patterned and etched to form a thin metal semiconductor alloy portion in the middle of the fuselink, while thick metal semiconductor alloy portions are formed on the end portions of the fuselink. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink to enhance the divergence of electrical current.
摘要翻译：在包含阴极半导体部分，熔丝半导体部分和阳极半导体部分的图案化的半导体材料层上沉积金属层。可以对金属层进行图案化，使得熔融半导体部分的中间部分具有薄金属层，其在退火时产生比在熔融半导体部分上的周围金属半导体合金部分更薄的金属半导体合金部分。或者，在整个整体中具有均匀厚度的金属半导体合金的中间部分可以被光刻图案化和蚀刻，以在熔丝中间形成薄金属半导体合金部分，同时在端部形成厚金属半导体合金部分的fuselink。所产生的本发明的电熔丝具有界面，在该界面上，较薄的金属半导体合金与所述富熔体中较厚的金属半导体合金相接触以增强电流的发散。

7. 发明申请

US20090096059A1 FUSE STRUCTURE INCLUDING MONOCRYSTALLINE SEMICONDUCTOR MATERIAL LAYER AND GAP 有权
标题翻译：保险丝结构，包括单晶半导体材料层和GAP
公开(公告)号：US20090096059A1
公开(公告)日：2009-04-16
申请号：US11870007
申请日：2007-10-10
申请人： Anil Kumar Chinthakindi , Deok-kee Kim , Chandrasekharan Kothandaraman , Byeongju Park
发明人： Anil Kumar Chinthakindi , Deok-kee Kim , Chandrasekharan Kothandaraman , Byeongju Park
IPC分类号： H01L29/00 , H01L21/02
CPC分类号： H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure, a method for fabricating the fuse structure and a method for programming a fuse within the fuse structure each use a fuse material layer that is used as a fuse, and located upon a monocrystalline semiconductor material layer in turn located over a substrate. At least part of the monocrystalline semiconductor material layer is separated from the substrate by a gap. Use of the monocrystalline semiconductor material layer, as well as the gap, provides for enhanced uniformity and reproducibility when programming the fuse.
摘要翻译：熔丝结构，制造熔丝结构的方法和用于对熔丝结构内的熔丝进行编程的方法各自使用用作熔丝的熔丝材料层，并且依次位于单晶半导体材料层上而位于衬底上。至少部分单晶半导体材料层通过间隙与衬底分离。单晶半导体材料层的使用以及间隙，在编程保险丝时提供了增强的均匀性和再现性。

8. 发明申请

US20090042341A1 ELECTRICAL FUSE WITH A THINNED FUSELINK MIDDLE PORTION 失效
标题翻译：带有薄型熔断器中间部分的电气保险丝
公开(公告)号：US20090042341A1
公开(公告)日：2009-02-12
申请号：US11835800
申请日：2007-08-08
申请人： Dureseti Chidambarrao , William K. Henson , Deok-kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semiconductor portion has a thin metal layer, which upon annealing produces a thinner metal semiconductor alloy portion than surrounding metal semiconductor alloy portion on the fuselink semiconductor portion. Alternatively, a middle portion of the metal semiconductor alloy having a uniform thickness throughout the fuselink may be lithographically patterned and etched to form a thin metal semiconductor alloy portion in the middle of the fuselink, while thick metal semiconductor alloy portions are formed on the end portions of the fuselink. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink to enhance the divergence of electrical current.
摘要翻译：在包含阴极半导体部分，熔丝半导体部分和阳极半导体部分的图案化的半导体材料层上沉积金属层。可以对金属层进行图案化，使得熔融半导体部分的中间部分具有薄金属层，其在退火时产生比在熔融半导体部分上的周围金属半导体合金部分更薄的金属半导体合金部分。或者，在整个整体中具有均匀厚度的金属半导体合金的中间部分可以被光刻图案化和蚀刻，以在熔丝中间形成薄金属半导体合金部分，同时在端部形成厚金属半导体合金部分的fuselink。所产生的本发明的电熔丝具有界面，在该界面上，较薄的金属半导体合金与所述富熔体中较厚的金属半导体合金相接触以增强电流的发散。

9. 发明申请

US20080169529A1 EFUSE CONTAINING SIGE STACK 有权
标题翻译： EFUSE包含信号堆栈
公开(公告)号：US20080169529A1
公开(公告)日：2008-07-17
申请号：US11622616
申请日：2007-01-12
申请人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
发明人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

10. 发明申请

US20080079113A1 FUSE STRUCTURE INCLUDING CAVITY AND METHODS FOR FABRICATION THEREOF 失效
标题翻译：包括密封的保险丝结构及其制造方法
公开(公告)号：US20080079113A1
公开(公告)日：2008-04-03
申请号：US11538170
申请日：2006-10-03
申请人： Anil K. Chinthakindi , Deok-kee Kim , Chandrasekharan Kothandaraman
发明人： Anil K. Chinthakindi , Deok-kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure comprises a cavity interposed between a substrate and a fuse material layer. The cavity is not formed at a sidewall of the fuse material layer, or at a surface of the fuse material layer opposite the substrate. A void may be formed interposed between the substrate and the fuse material layer while using a self-aligned etching method, when the fuse material layer comprises lobed ends and a narrower middle region. The void is separated by a pair of sacrificial layer pedestals that support the fuse material layer. The void is encapsulated to form the cavity by using an encapsulating dielectric layer. Alternatively, a block mask may be used when forming the void interposed between the substrate and the fuse material layer.
摘要翻译：熔丝结构包括插入在基板和熔丝材料层之间的空腔。空腔不形成在熔丝材料层的侧壁处，或者在与衬底相对的熔丝材料层的表面处。当熔丝材料层包括裂纹末端和较窄的中间区域时，可以在使用自对准蚀刻方法的同时在衬底和熔丝材料层之间形成空隙。空隙由支撑熔丝材料层的一对牺牲层基座分开。通过使用封装介电层将空隙封装以形成空腔。或者，当形成插入在基板和熔丝材料层之间的空隙时，可以使用块掩模。

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