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1. 发明授权

US07927994B1 Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing 有权
标题翻译：具有浮置栅极，控制栅极，选择栅极和具有悬垂在浮动栅极上的擦除栅极的分流门非易失性闪存单元，阵列和制造方法
公开(公告)号：US07927994B1
公开(公告)日：2011-04-19
申请号：US12961193
申请日：2010-12-06
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： H01L21/4763
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译：改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间和底物中的第二区域。单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。擦除栅极具有在浮动栅极上延伸的突出端。悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

2. 发明申请

US20090039410A1 Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing 审中-公开
标题翻译：分闸门非挥发性闪存单元，具有浮动栅极，控制栅极，选择栅极和具有悬垂在浮栅上的擦除栅极，阵列和制造方法
公开(公告)号：US20090039410A1
公开(公告)日：2009-02-12
申请号：US11834574
申请日：2007-08-06
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： H01L29/788
CPC分类号： H01L29/42328 , H01L27/11521 , H01L29/40114 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译：改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间和底物中的第二区域。单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。擦除栅极具有在浮动栅极上延伸的突出端。悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

3. 发明申请

US20110076816A1 SPLIT GATE NON-VOLATILE FLASH MEMORY CELL HAVING A FLOATING GATE, CONTROL GATE, SELECT GATE AND AN ERASE GATE WITH AN OVERHANG OVER THE FLOATING GATE, ARRAY AND METHOD OF MANUFACTURING 有权
标题翻译：分离闸门具有浮动门，控制门，选择门和在浮动门，阵列和制造方法上的过滤器的非挥发性闪存存储单元
公开(公告)号：US20110076816A1
公开(公告)日：2011-03-31
申请号：US12961193
申请日：2010-12-06
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译：改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间和底物中的第二区域。单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。擦除栅极具有在浮动栅极上延伸的突出端。悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

4. 发明授权

US07868375B2 Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing 有权
公开(公告)号：US07868375B2
公开(公告)日：2011-01-11
申请号：US12618632
申请日：2009-11-13
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien Sheng Su , Yaw Wen Hu
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

5. 发明申请

US20110127599A1 Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing 审中-公开
标题翻译：具有浮动门的分闸门非易失性闪存单元，控制门，选择门和具有悬浮在浮动门上的擦除门，阵列和制造方法
公开(公告)号：US20110127599A1
公开(公告)日：2011-06-02
申请号：US13023443
申请日：2011-02-08
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： H01L29/788
CPC分类号： H01L29/42328 , H01L27/11521 , H01L29/40114 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译：改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间和底物中的第二区域。单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。擦除栅极具有在浮动栅极上延伸的突出端。悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

6. 发明申请

US20100054043A1 Split Gate Non-Volatile Flash Memory Cell Having a Floating Gate, Control Gate, Select Gate and an Erase Gate with an Overhang Over the Floating Gate, Array and Method of Manufacturing 有权
标题翻译：具有浮动门的分流门非易失性闪存单元，控制栅极，选择栅极和擦除栅极，在浮动栅极上的突出，阵列和制造方法
公开(公告)号：US20100054043A1
公开(公告)日：2010-03-04
申请号：US12618632
申请日：2009-11-13
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： G11C16/04 , H01L21/336 , G11C11/34 , H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译：改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间和底物中的第二区域。单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。擦除栅极具有在浮动栅极上延伸的突出端。悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

7. 发明授权

US09466732B2 Split-gate memory cell with depletion-mode floating gate channel, and method of making same 有权
标题翻译：具有耗尽型浮动栅极通道的分离栅极存储单元及其制造方法
公开(公告)号：US09466732B2
公开(公告)日：2016-10-11
申请号：US13593460
申请日：2012-08-23
申请人： Yuri Tkachev
发明人： Yuri Tkachev
IPC分类号： H01L21/04 , H01L29/788 , H01L21/28 , H01L29/423 , H01L29/66 , G11C16/04
CPC分类号： H01L29/7885 , G11C16/0425 , H01L21/28273 , H01L29/42328 , H01L29/66825
摘要： A memory device having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and wherein at least a portion of the channel region first portion is of the second conductivity type.
摘要翻译：一种存储器件，具有第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，衬底中的沟道区域，与衬底绝缘的导电浮动栅极，其中所述浮动栅极至少部分地设置在所述沟道区域的第一部分和所述沟道区域的第一部分之上，与所述浮动栅极横向相邻并与所述浮动栅极绝缘的导电第二栅极，其中所述第二栅极至少部分地设置在所述浮置栅极上并与其绝缘沟道区的第二部分，并且其中沟道区第一部分的至少一部分是第二导电类型。

8. 发明申请

US20130121085A1 Method Of Operating A Split Gate Flash Memory Cell With Coupling Gate 有权
标题翻译：使用耦合栅极操作分离栅极闪存单元的方法
公开(公告)号：US20130121085A1
公开(公告)日：2013-05-16
申请号：US13463558
申请日：2012-05-03
申请人： Nhan Do , Elizabeth A. Cuevas , Yuri Tkachev , Mandana Tadayoni , Henry A. Om'Mani
发明人： Nhan Do , Elizabeth A. Cuevas , Yuri Tkachev , Mandana Tadayoni , Henry A. Om'Mani
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C16/0433 , G11C16/14 , H01L27/115
摘要： A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.
摘要翻译：一种操作存储单元的方法，所述存储单元包括在衬底中间隔开的沟道区域的第一和第二区域，设置在所述沟道区域和所述第一区域上方的浮置栅极，设置在所述沟道区域上并横向邻近所述第二区域的方法浮动栅极，其具有设置在浮置栅极上的部分，以及耦合栅极，设置在第一区域上并且横向邻近浮动栅极。擦除存储单元的方法包括向控制栅极施加正电压，向耦合栅极施加负电压。读取存储单元的方法包括向控制栅极，耦合栅极以及第一和第二区域之一施加正电压。

9. 发明申请

US20140054667A1 Split-Gate Memory Cell With Depletion-Mode Floating Gate Channel, And Method Of Making Same 有权
标题翻译：具有耗尽型浮动门通道的分离门存储单元及其制作方法
公开(公告)号：US20140054667A1
公开(公告)日：2014-02-27
申请号：US13593460
申请日：2012-08-23
申请人： Yuri Tkachev
发明人： Yuri Tkachev
IPC分类号： H01L29/788 , H01L21/04
CPC分类号： H01L29/7885 , G11C16/0425 , H01L21/28273 , H01L29/42328 , H01L29/66825
摘要： A memory device having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and wherein at least a portion of the channel region first portion is of the second conductivity type.
摘要翻译：一种存储器件，具有第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，衬底中的沟道区域，与衬底绝缘的导电浮动栅极，其中所述浮动栅极至少部分地设置在所述沟道区域的第一部分和所述沟道区域的第一部分之上，与所述浮动栅极横向相邻并与所述浮动栅极绝缘的导电第二栅极，其中所述第二栅极至少部分地设置在所述浮置栅极上并与其绝缘沟道区的第二部分，并且其中沟道区第一部分的至少一部分是第二导电类型。

10. 发明授权

US08711636B2 Method of operating a split gate flash memory cell with coupling gate 有权
标题翻译：操作具有耦合栅极的分离栅极闪存单元的方法
公开(公告)号：US08711636B2
公开(公告)日：2014-04-29
申请号：US13463558
申请日：2012-05-03
申请人： Nhan Do , Elizabeth A. Cuevas , Yuri Tkachev , Mandana Tadayoni , Henry A. Om'Mani
发明人： Nhan Do , Elizabeth A. Cuevas , Yuri Tkachev , Mandana Tadayoni , Henry A. Om'Mani
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/0433 , G11C16/14 , H01L27/115
摘要： A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.
摘要翻译：一种操作存储单元的方法，所述存储单元包括在衬底中间隔开的沟道区域的第一和第二区域，设置在所述沟道区域和所述第一区域上方的浮置栅极，设置在所述沟道区域上并横向邻近所述第二区域的方法浮动栅极，其具有设置在浮置栅极上的部分，以及耦合栅极，设置在第一区域上并且横向邻近浮动栅极。擦除存储单元的方法包括向控制栅极施加正电压，向耦合栅极施加负电压。读取存储单元的方法包括向控制栅极，耦合栅极以及第一和第二区域之一施加正电压。

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