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1. 发明授权

US06998306B2 Semiconductor memory device having a multiple tunnel junction pattern and method of fabricating the same 失效
公开(公告)号：US06998306B2
公开(公告)日：2006-02-14
申请号：US10747449
申请日：2003-12-30
申请人： Woo-Sik Kim , Ji-Hye Yi
发明人： Woo-Sik Kim , Ji-Hye Yi
IPC分类号： H01L21/8234
CPC分类号： H01L27/108 , Y10S257/903 , Y10S257/904
摘要： The present invention discloses a semiconductor memory device having a multiple tunnel junction pattern and a method of forming the same. The semiconductor memory device includes a unit cell composed of planar transistor and vertical transistors. The planar transistor includes first and second conductive regions formed at predetermined regions of a semiconductor substrate and a storage node stacked on a channel region therebetween. The vertical transistor includes a storage node, a multiple tunnel junction pattern stacked thereon, a data line stacked thereon, and a word line for covering both sidewalls of the storage node and the multiple tunnel junction pattern. Width of the multiple tunnel junction pattern is narrower than the storage node and data lines. Semiconductor layers and tunnel oxide layers are alternately and repeatedly stacked and anisotropically etched to form the multiple tunnel junction pattern of narrow width while forming the data line and the storage node.

2. 发明授权

US06635921B2 Semiconductor memory device having a multiple tunnel junction layer pattern and method of fabricating the same 有权
公开(公告)号：US06635921B2
公开(公告)日：2003-10-21
申请号：US10146897
申请日：2002-05-17
申请人： Ji-Hye Yi , Woo-Sik Kim
发明人： Ji-Hye Yi , Woo-Sik Kim
IPC分类号： H01L29788
CPC分类号： H01L21/28273 , H01L21/32134 , H01L27/11521 , H01L29/42324 , H01L29/7881 , H01L29/88
摘要： A semiconductor memory device and fabricating method thereof, wherein the semiconductor memory device includes first and second conductive regions formed in parallel at predetermined regions of a semiconductor substrate, a storage node and a multiple tunnel junction layer pattern sequentially stacked on a channel region between the first and second conductive regions, a data line stacked on the multiple tunnel junction layer pattern, and a wordline covering both sidewalls of the storage node and of the multiple tunnel junction layer pattern, wherein both sidewalls of the storage node have undercut regions for increasing the overlapping area of the storage node and a wordline. The storage node is formed by alternately and repeatedly stacking first and second conductive layers having different etch rates, successively patterning the conductive layers to form a storage node pattern, and selectively and isotropically etching the first or second conductive layer of the storage node pattern.

3. 发明授权

US06686240B2 Semiconductor memory device having a multiple tunnel junction layer pattern and method of fabricating the same 失效
标题翻译：具有多重隧道结层图案的半导体存储器件及其制造方法
公开(公告)号：US06686240B2
公开(公告)日：2004-02-03
申请号：US10394030
申请日：2003-03-24
申请人： Ji-Hye Yi , Woo-Sik Kim
发明人： Ji-Hye Yi , Woo-Sik Kim
IPC分类号： H01L218242
CPC分类号： H01L21/28273 , H01L21/32134 , H01L27/11521 , H01L29/42324 , H01L29/7881 , H01L29/88
摘要： A semiconductor memory device and fabricating method thereof, wherein the semiconductor memory device includes first and second conductive regions formed in parallel at predetermined regions of a semiconductor substrate, a storage node and a multiple tunnel junction layer pattern sequentially stacked on a channel region between the first and second conductive regions, a data line stacked on the multiple tunnel junction layer pattern, and a wordline covering both sidewalls of the storage node and of the multiple tunnel junction layer pattern, wherein both sidewalls of the storage node have undercut regions for increasing the overlapping area of the storage node and a wordline. The storage node is formed by alternately and repeatedly stacking first and second conductive layers having different etch rates, successively patterning the conductive layers to form a storage node pattern, and selectively and isotropically etching the first or second conductive layer of the storage node pattern.
摘要翻译：一种半导体存储器件及其制造方法，其中半导体存储器件包括在半导体衬底，存储节点和多个隧道结层图案的预定区域处并行形成的第一和第二导电区域，以及第二导电区域，堆叠在所述多个隧道结层图案上的数据线，以及覆盖所述存储节点和所述多重隧道结层图案的两个侧壁的字线，其中所述存储节点的两个侧壁具有用于增加所述重叠的底切区域存储节点的区域和字线。存储节点通过交替地且重复地堆叠具有不同蚀刻速率的第一和第二导电层，连续地图案化导电层以形成存储节点图案，并且选择性地和各向同性地蚀刻存储节点图案的第一或第二导电层。

4. 发明授权

US06707089B2 Semiconductor memory device having a multiple tunnel junction pattern and method of fabricating the same 失效
公开(公告)号：US06707089B2
公开(公告)日：2004-03-16
申请号：US10260387
申请日：2002-10-01
申请人： Woo-Sik Kim , Ji-Hye Yi
发明人： Woo-Sik Kim , Ji-Hye Yi
IPC分类号： H01L27108
CPC分类号： H01L27/108 , Y10S257/903 , Y10S257/904
摘要： The present invention discloses a semiconductor memory device having a multiple tunnel junction pattern and a method of forming the same. The semiconductor memory device includes a unit cell composed of planar transistor and vertical transistors. The planar transistor includes first and second conductive regions formed at predetermined regions of a semiconductor substrate and a storage node stacked on a channel region therebetween. The vertical transistor includes a storage node, a multiple tunnel junction pattern stacked thereon, a data line stacked thereon, and a word line for covering both sidewalls of the storage node and the multiple tunnel junction pattern. Width of the multiple tunnel junction pattern is narrower than the storage node and data lines. Semiconductor layers and tunnel oxide layers are alternately and repeatedly stacked and anisotropically etched to form the multiple tunnel junction pattern of narrow width while forming the data line and the storage node.

5. 发明授权

US08426916B2 Semiconductor integrated circuit devices having different thickness silicon-germanium layers 有权
标题翻译：具有不同厚度的硅 - 锗层的半导体集成电路器件
公开(公告)号：US08426916B2
公开(公告)日：2013-04-23
申请号：US13476121
申请日：2012-05-21
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/36
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
摘要翻译：提供制造半导体集成电路器件的方法。基板设置有形成在第一和第二区域上的栅极图案。第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。第二SiGe外延层直接形成在第一SiGe外延层上，以使用不同于第一硅源气体的第二硅源气体来进一步填充源极/漏极沟槽。

6. 发明授权

US08207033B2 Methods of fabricating different thickness silicon-germanium layers on semiconductor integrated circuit devices and semiconductor integrated circuit devices fabricated thereby 有权
标题翻译：在半导体集成电路器件上制造不同厚度的硅 - 锗层的方法和由此制造的半导体集成电路器件
公开(公告)号：US08207033B2
公开(公告)日：2012-06-26
申请号：US12419698
申请日：2009-04-07
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
摘要翻译：提供制造半导体集成电路器件的方法。基板设置有形成在第一和第二区域上的栅极图案。第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。直接在第一SiGe外延层上形成第二SiGe外延层，以使用不同于第一硅源气体的第二硅源气体来进一步填充源/漏沟槽。

7. 发明申请

US20120228720A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES HAVING DIFFERENT THICKNESS SILICON-GERMANIUM LAYERS 有权
标题翻译：具有不同厚度硅 - 锗层的半导体集成电路器件
公开(公告)号：US20120228720A1
公开(公告)日：2012-09-13
申请号：US13476121
申请日：2012-05-21
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
IPC分类号： H01L27/088
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
摘要翻译：提供制造半导体集成电路器件的方法。基板设置有形成在第一和第二区域上的栅极图案。第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。直接在第一SiGe外延层上形成第二SiGe外延层，以使用不同于第一硅源气体的第二硅源气体来进一步填充源/漏沟槽。

8. 发明申请

US20100006906A1 Semiconductor device, single crystalline silicon wafer, and single crystalline silicon ingot 审中-公开
标题翻译：半导体器件，单晶硅晶片和单晶硅锭
公开(公告)号：US20100006906A1
公开(公告)日：2010-01-14
申请号：US12458500
申请日：2009-07-14
申请人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
发明人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
IPC分类号： H01L29/04
CPC分类号： H01L27/0203 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L29/045 , H01L29/66628
摘要： A semiconductor device includes a single crystalline substrate and an active region defined in the single crystalline substrate, wherein a major axis direction of the active region is aligned with a family direction.
摘要翻译：半导体器件包括单晶衬底和限定在单晶衬底中的有源区，其中有源区的长轴方向与<0,1,1>族方向对齐。

9. 发明授权

US07569430B2 Phase changeable structure and method of forming the same 有权
标题翻译：相变结构及其形成方法
公开(公告)号：US07569430B2
公开(公告)日：2009-08-04
申请号：US11674580
申请日：2007-02-13
申请人： Jun-Soo Bae , Hideki Horii , Ji-Hye Yi , Young-Soo Lim
发明人： Jun-Soo Bae , Hideki Horii , Ji-Hye Yi , Young-Soo Lim
IPC分类号： H01L21/82
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： The present invention relates to a phase changeable structure having decreased amounts of defects and a method of forming the phase changeable structure. A stacked composite is first formed by (i) forming a phase changeable layer including a chalcogenide is formed on a lower electrode, (ii) forming an etch stop layer having a first etch rate with respect to a first etching material including chlorine on the phase changeable layer, and (iii) forming a conductive layer having a second etch rate with respect to the first etching material on the etch stop layer. The conductive layer of the stacked composite is then etched using the first etching material to form an upper electrode. The etch stop layer and the phase changeable layer are then etched using a second etching material that is substantially flee of chlorine to form an etch stop pattern and a phase changeable pattern, respectively.
摘要翻译：本发明涉及具有减少的缺陷量的相变结构和形成相变结构的方法。首先通过（i）在下电极上形成包括硫族化物的相变层来形成堆叠复合体，（ii）形成相对于在相上包括氯的第一蚀刻材料具有第一蚀刻速率的蚀刻停止层可变层，和（iii）形成相对于蚀刻停止层上的第一蚀刻材料具有第二蚀刻速率的导电层。然后使用第一蚀刻材料蚀刻层叠复合体的导电层以形成上电极。然后使用基本上不含氯的第二蚀刻材料来蚀刻蚀刻停止层和相变层，以分别形成蚀刻停止图案和相变图案。

10. 发明申请

US20090170254A1 Method of Manufacturing a Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090170254A1
公开(公告)日：2009-07-02
申请号：US12343134
申请日：2008-12-23
申请人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
发明人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are formed in the first area of the substrate adjacent the first gate electrode. A layer having a first stress is formed on the substrate and the first and the second gate electrodes. A mask is formed on a first portion of the layer in the first area of the substrate to expose a second portion of the layer in the second area. The second portion is etched to form a sacrificial spacer on a sidewall of the second gate electrode. The second area of the substrate is partially etched using the mask, the second gate electrode and the sacrificial spacer, to form recesses in the second area of the substrate adjacent the second gate electrode. Patterns having a second stress are formed in the recesses.
摘要翻译：在制造半导体器件的方法中，第一栅电极和第二栅电极形成在衬底的第一区域和第二区域中。在与第一栅电极相邻的衬底的第一区域中形成非结晶区域。在基板和第一和第二栅电极上形成具有第一应力的层。掩模在衬底的第一区域中的该层的第一部分上形成以暴露第二区域中该层的第二部分。蚀刻第二部分以在第二栅电极的侧壁上形成牺牲间隔物。使用掩模，第二栅电极和牺牲隔离物部分蚀刻衬底的第二区域，以在与第二栅电极相邻的衬底的第二区域中形成凹陷。在凹部中形成具有第二应力的图案。

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